Semiconductor Via Profile Shaping for Lower Resistance
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Solution Overview
Problem
The semiconductor industry faces challenges in forming vias with optimal dimensions for FinFETs, as existing methods result in vias with tapered profiles, leading to increased resistance and suboptimal performance.
Innovation Solution
The method involves etching the upper interlayer dielectric layer to form a via opening and then using H2 as a carrier gas to enhance lateral etching of the etching stop layer, resulting in a via with a wide bottom portion, thereby reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to form vias, then the via opening can be formed through the interlayer dielectric layer, but the via develops a tapered profile with increased resistance
Solution Approach 1:
The patent changes the etching process parameters by introducing H2 as a carrier gas and adjusting the etching chemistry to achieve different lateral etching rates at different depths. This parameter change transforms the conventional tapered via profile into a plug-like profile with wider bottom portion, directly resolving the contradiction between profile control and resistance reduction
Solution Approach 2:
The etching process is divided into multiple stages with different gas compositions and flow rates. The process transitions from an initial etching stage to a final etching stage, where H2 is introduced to enhance lateral etching at the bottom portion. This periodic action allows precise control over the via profile development, achieving both profile control and reduced resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of semiconductor devices by lowering the resistance of the vias, enhancing the speed and efficiency of the resulting semiconductor structure.
Implementation Method 1
using H2 as a carrier gas to enhance lateral etching of the etching stop layer, resulting in a via with a wide bottom portion
Data Source
AI summary
A method includes forming a conductive feature through a first dielectric layer, sequentially forming a second dielectric layer and a third dielectric layer over the first dielectric layer, and etching the third dielectric layer to form an opening. A first width of the opening at a top surface of the third dielectric layer is greater than a second width of the opening at a first interface between the third dielectric layer and the second dielectric layer. The method also includes etching the second dielectric layer until the opening extends to the conductive feature, thereby forming an enlarged opening, and forming a metal material in the enlarged opening. A third width of the enlarged opening at the first interface is equal to or less than a fourth width of the enlarged opening at a second interface between the second dielectric layer and the first dielectric layer.