ONNO Memory Transistor Stack for Data Retention and CMOS Integration
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Solution Overview
Problem
Conventional memory transistors suffer from poor data retention and limited transistor lifetime due to leakage currents through insulating layers, and existing processes for forming memory transistors are often incompatible with those used for logic transistors in integrated circuits, particularly in System-On-Chip applications.
Innovation Solution
A memory transistor with a polysilicon channel region and an oxide-nitride-nitride-oxide (ONNO) stack, including a multi-layer charge-trapping region with an oxygen-rich first nitride layer and an oxygen-lean second nitride layer, along with a high work function gate electrode, is used to enhance data retention and compatibility with logic transistor fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional charge trapping layer is used in memory transistors, then the initial program-erase window is achieved, but data retention deteriorates over time due to leakage current
Solution Approach 1:
The charge trapping layer is divided into multiple discrete trapping sites within the oxide layer, creating separate energy levels for charge storage. This segmentation prevents charge leakage by confining electrons in localized potential wells, thereby improving data retention while maintaining the program-erase window.
Solution Approach 2:
The patent employs a composite structure combining oxide layers with embedded nitride trapping sites to form the charge storage region. This composite material approach leverages the insulating properties of oxide and the charge-trapping capability of nitride, achieving both good retention and sufficient initial window.
2Reliability
If the charge trapping layer is made silicon-rich to increase trap density, then the initial program-erase window increases, but data retention collapses rapidly
Solution Approach 1:
The patent creates localized trapping sites with high trap density within an otherwise stoichiometric or silicon-lean oxide matrix. This local quality approach concentrates charge trapping capability in specific regions while maintaining overall oxide integrity, achieving both large program-erase window and good retention.
Solution Approach 2:
The patent modifies the chemical composition parameters of the charge trapping layer by incorporating nitrogen into the oxide structure, creating oxynitride or silicon oxynitride layers. This parameter change adjusts the band structure and trap energy levels, enabling simultaneous achievement of large window and good retention.
3Ease of manufacture
If conventional memory transistor processes are used, then manufacturing simplicity is maintained, but compatibility with logic transistor processes is poor
Solution Approach 1:
The patent designs a charge trapping layer using oxide and nitride materials that can be deposited using standard CMOS-compatible processes such as PECVD and sputtering. This universality allows the same fabrication line to produce both logic and memory transistors, enabling System-On-Chip integration without requiring separate manufacturing facilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly improves data retention and extends the operating life of memory transistors by reducing charge loss and leakage currents, while allowing for the integration of both memory and logic transistors on a common substrate, enhancing the performance and efficiency of integrated circuits.
Implementation Method 1
A programming voltage applied to the control gate traps a charge on the charge trapping layer, partially canceling or screening an electric field from the control gate
Implementation Method 2
A programming voltage applied to the control gate traps a charge on the charge trapping layer, partially canceling or screening an electric field from the control gate
Data Source
AI summary
An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.