Core-Shell GaN Nanofin Vertical Switch for High-Voltage Breakdown Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional GaN transistors with vertical architecture face challenges in high-voltage switching due to difficulties in producing lateral p-n junctions, leading to high electrical leakage currents and low-voltage breakdown, especially in power electronics applications.
Innovation Solution
A core-shell nanofin vertical switch is developed, comprising an n-type GaN nanofin core and a p-type nanofin shell, allowing for high-voltage switching with low on-state resistance and normally-off operation, using epitaxial growth to create a fin-based geometry that avoids contamination and defects associated with etch-and-regrowth processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etch-and-regrowth processes are used to produce lateral p-n junctions in vertical GaN transistors, then the device structure can be formed, but high electrical leakage currents and low-voltage breakdown occur due to contamination and defects
Solution Approach 1:
The device is segmented into a vertical architecture with separate source, drain, and gate regions arranged vertically rather than laterally. This segmentation eliminates the need for lateral p-n junctions and their associated contamination problems, while maintaining the essential transistor functionality through vertical current flow control.
Solution Approach 2:
The conventional lateral p-n junction structure is inverted to a vertical configuration. Instead of forming p-n junctions horizontally across the substrate, the invention uses vertical stacking of doped regions and electric fields to achieve the same switching function without the contamination issues of lateral junction formation.
2Reliability
If lateral p-n junctions are produced in vertical GaN transistors, then the transistor structure can be completed, but the device suffers from low-voltage breakdown
Solution Approach 1:
The invention transitions from two-dimensional lateral p-n junction formation to three-dimensional vertical structure formation. By utilizing the vertical dimension for current flow and field control, the device achieves higher breakdown voltage without the complexity of lateral junction engineering, as the vertical field distribution can be more effectively controlled.
3Ease of operation
If conventional vertical GaN transistor structures are used, then the device can operate, but high electrical leakage currents occur due to contamination from etch-and-regrowth processes
Solution Approach 1:
The harmful etch-and-regrowth process step is extracted and eliminated from the fabrication sequence. The invention uses a direct vertical growth approach that takes out the intermediate lateral junction formation step, thereby removing the source of contamination that generates electrical leakage currents while preserving the switching operation capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The core-shell nanofin vertical switch achieves high-voltage switching with low on-state resistance and reliable operation, suitable for power electronics, such as converters and motor drivers, by utilizing a superjunction structure that withstands high source-drain voltages without electrical breakdown.
Implementation Method 1
accumulating electron charge carriers in the n-type GaN nanofin core in response to receiving the gate voltage; depleting the electron charge carriers from the n-type GaN nanofin core in response to receiving the gate voltage at ground potential or negative with respect to a ground potential
Data Source
AI summary
A core-shell nanofin vertical switch performs high-voltage switching and includes: an n-type GaN nanofin core including: an n-type drift layer; an n-type channel; and an n-type source; a p-type nanofin shell surrounding the n-type GaN nanofin core at an interface surface of the n-type GaN nanofin core, and comprising GaN; an optional source contact disposed on the n-type GaN nanofin core and the p-type nanofin shell and in electrical communication with the n-type source, such that the n-type source is interposed between the source contact and the n-type channel; and a gate contact disposed on the p-type nanofin shell and in electrical communication with the p-type nanofin shell, such that the p-type nanofin shell is interposed between the gate contact and the n-type channel, and the gate contact is interposed between the source contact and a drain contact.