Stacked Fin Structure Layout for Independent GAA Gate Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor technologies face challenges in scaling down while maintaining gate control and reducing short-channel effects, particularly in planar GAA finFETs, due to identical nanosheet/nanowire dimensions and spacings for n-type and p-type devices, which affect threshold voltage and performance.
Innovation Solution
The development of vertically stacked and crossover-stacked semiconductor devices with independently controllable fin structures and gate orientations, allowing for distinct nanosheet/nanowire dimensions and spacings, as well as rotated gate structures to improve metal interconnects and reduce parasitic resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar GAA finFETs with identical nanosheet/nanowire dimensions are used for both n-type and p-type devices, then manufacturing process is simplified, but work function metal fill flexibility is reduced and threshold voltage boundary shifts occur during etching
Solution Approach 1:
The patent divides the previously uniform fin structure into separate top and bottom fin structures with independently controllable dimensions and spacings. This segmentation allows n-type and p-type devices to have optimized nanosheet/nanowire configurations tailored to their specific electrical requirements, thereby restoring work function metal fill flexibility without complicating the overall manufacturing process
Solution Approach 2:
The patent implements local quality by allowing different regions (top and bottom fins) to have different nanosheet/nanowire dimensions and spacings. This enables each region to be optimized for its specific device type (n-type or p-type), providing local adaptability in work function metal fill while maintaining a unified manufacturing approach
2Device complexity
If planar GAA finFETs with identical nanosheet/nanowire dimensions are used, then device structure is simplified, but threshold voltage boundary shifts occur during etching leading to performance degradation
Solution Approach 1:
By segmenting the fin structure into top and bottom portions with independent dimensional control, the patent eliminates the threshold voltage boundary shift problem that occurs in uniform structures during etching. Each segment can be independently optimized to maintain stable threshold voltages, improving reliability without significantly increasing overall device complexity
Solution Approach 2:
The patent applies preliminary action by pre-defining isolation layers between top and bottom fin structures before etching operations. This preliminary structural preparation prevents threshold voltage boundary shifts during subsequent etching processes, ensuring stable device performance
3Area of stationary object
If vertically stacked or crossover-stacked structures with additional isolation layers are implemented, then device area efficiency is improved by 30% to 50%, but manufacturing process complexity increases
Solution Approach 1:
The patent transitions from planar to vertically stacked or crossover-stacked configurations, utilizing the vertical dimension to achieve higher device density. This dimensional change reduces the footprint area by 30% to 50% while the added isolation layers and independent fin structures are integrated into the manufacturing process using extended versions of existing techniques
4Loss of energy
If vertically stacked or crossover-stacked structures are implemented, then parasitic resistance and capacitance are reduced improving PPA performance, but device structure complexity increases
Solution Approach 1:
By moving to vertically stacked or crossover-stacked architectures, the patent reduces the horizontal spacing between interconnects and active devices, thereby reducing parasitic resistance and capacitance. The improved PPA performance is achieved through this dimensional reorganization, with the increased vertical structure complexity offset by the benefits in electrical performance
Data Source
AI summary
The present disclosure describes a semiconductor device includes a first fin structure, an isolation structure in contact with a top surface of the first fin structure, a substrate layer in contact with the isolation structure, an epitaxial layer in contact with the isolation structure and the substrate layer, and a second fin structure above the first fin structure and in contact with the epitaxial layer.