SiGe Source-Drain Capping Layer for Defect-Free PMOS Strain
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Solution Overview
Problem
Conventional integrated circuit fabrication processes face challenges in achieving high germanium concentration capping layers for source and drain structures, leading to crystallographic dislocations and compromised channel mobility, which limits further scaling to sub-10 nanometer nodes.
Innovation Solution
The method involves epitaxial deposition of a Ge:B layer capped with a thin low Ge concentration SiGe:B layer, followed by a high temperature anneal that melts and recrystallizes the Ge:B layer, resulting in a high Ge containing defect-free SiGe:B capping layer with high boron concentration, reducing contact resistivity and increasing channel strain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used to form source and drain structures, then manufacturing simplicity is maintained, but crystallographic dislocations occur and channel mobility is compromised
Solution Approach 1:
The source and drain structure is segmented into multiple layers: a lower semiconductor layer and a capping semiconductor layer with different germanium concentrations. This segmentation allows each layer to serve specific functions - the lower layer provides structural foundation while the capping layer with high germanium concentration enhances channel mobility without causing dislocations throughout the entire structure.
Solution Approach 2:
Different regions of the source and drain structure have different germanium concentrations tailored to specific functional requirements. The capping layer has high germanium concentration (greater than 50%) localized at the top region adjacent to the channel to maximize mobility enhancement, while the lower layer has lower germanium concentration to maintain structural stability and avoid dislocation formation.
2Reliability
If high germanium concentration is introduced in source and drain structures, then channel strain is increased, but crystallographic dislocations are generated
Solution Approach 1:
The capping layer with high germanium concentration is deposited first on the lower semiconductor layer before final epitaxial growth. This preliminary positioning of the high germanium layer allows it to induce channel strain in the overlying channel region without the high germanium material being present during subsequent epitaxial growth, thereby preventing dislocation formation that would occur if high germanium concentration material were grown during the epitaxial process.
Solution Approach 2:
The germanium concentration parameter is changed and optimized at different depths within the source and drain structure. By controlling the germanium concentration to be greater than 50% specifically in the capping layer while keeping it lower in the bulk source and drain regions, the patent achieves sufficient channel strain for high performance while avoiding the crystallographic dislocations that would result from uniformly high germanium concentration throughout the structure.
3Reliability
If germanium concentration is increased in capping layer, then contact resistivity is reduced, but fabrication difficulty increases
Solution Approach 1:
The epitaxial deposition process is divided into periodic stages with different germanium concentration settings. First, a lower germanium concentration is used to deposit the base semiconductor layer, then the germanium concentration is increased to deposit the high germanium capping layer. This periodic variation in deposition parameters enables precise control over the germanium concentration profile, achieving low contact resistivity through high germanium content while managing fabrication complexity through systematic process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of defect-free high Ge concentration capping layers, enhancing PMOS channel strain and reducing contact resistivity, thereby addressing the limitations of existing fabrication processes for advanced technology nodes.
Implementation Method 1
followed by a high temperature anneal that melts and recrystallizes the Ge:B layer
Implementation Method 2
followed by a high temperature anneal that melts and recrystallizes the Ge:B layer, resulting in a high Ge containing defect-free SiGe:B capping layer
Implementation Method 3
The method involves epitaxial deposition of a Ge:B layer capped with a thin low Ge concentration SiGe:B layer
Data Source
AI summary
Integrated circuit structures having source or drain structures with a high germanium concentration capping layer are described. In an example, an integrated circuit structure includes source or drain structures including an epitaxial structure embedded in a fin at a side of a gate stack. The epitaxial structure has a lower semiconductor layer and a capping semiconductor layer on the lower semiconductor layer with an abrupt interface between the capping semiconductor layer and the lower semiconductor layer. The lower semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of less than 40% at the abrupt interface. The capping semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of greater than 50% at the abrupt interface and throughout the capping semiconductor layer.