Forksheet Transistor Channel Depopulation for SRAM Drive Balance
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Solution Overview
Problem
The challenge in integrated circuit manufacturing lies in achieving balanced drive currents for forksheet transistors, particularly in SRAM cells, where conventional approaches often require assist circuitry to balance read stability and write-ability, leading to increased chip area and power consumption.
Innovation Solution
The implementation of forksheet transistors with depopulated channels allows for modulation of drive currents by selectively doping semiconductor channels, reducing the number of active channels in specific transistors to achieve better balance between read stability and write-ability without the need for assist circuits, using top-down or bottom-up depopulation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional tri-gate transistors are used with uniform channel doping, then manufacturing process is simpler, but drive current balance between pull-up and pull-down transistors is poor requiring assist circuitry
Solution Approach 1:
The patent applies local quality by implementing selective doping of specific channels in the forksheet transistor structure. The pull-down transistor has all channels doped while the pull-up transistor has the top channel undoped, creating local variations in electrical properties to balance drive currents without requiring assist circuitry
2Reliability
If assist circuitry is added to balance drive currents, then read stability and write-ability are improved, but chip area and power consumption increase
Solution Approach 1:
The patent extracts the need for assist circuitry by implementing drive current balance directly in the transistor structure through selective channel doping. This removes the harmful element (assist circuitry) and achieves the desired performance balance using only the forksheet transistor modification
3Productivity
If feature size is scaled down to increase device density, then capacity is improved, but lithographic process constraints become overwhelming
Solution Approach 1:
The patent transitions from planar transistor design to a three-dimensional forksheet structure with multiple vertically stacked channels. This dimensional change allows increased device density without proportionally increasing lithographic complexity, as the additional channels are formed through vertical stacking rather than lateral patterning
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the drive strength of certain transistors, eliminating the need for assist circuits, thereby saving chip area and power consumption while enhancing the balance between read stability and write-ability in SRAM cells.
Implementation Method 1
selectively doping semiconductor channels, reducing the number of active channels in specific transistors
Data Source
AI summary
Embodiments disclosed herein include forksheet transistor devices with depopulated channels. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to a first edge of the backbone. The first vertical stack of semiconductor channels includes first semiconductor channels and a second semiconductor channel over or beneath the first semiconductor channels. A concentration of a dopant in the first semiconductor channels is less than a concentration of the dopant in the second semiconductor channel. A second transistor device includes a second vertical stack of semiconductor channels adjacent to a second edge of the backbone opposite the first edge.