Buried Conductive Pad in STI for GAA Gate Routing Density
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Solution Overview
Problem
As semiconductor device feature sizes decrease, there is a growing challenge in optimizing circuit layouts due to space constraints, particularly in integrating buried conductive pads within isolation structures without interfering with fin-based transistor structures, which limits routing flexibility and increases area requirements.
Innovation Solution
The implementation of a gate-all-around transistor structure electrically coupled to a buried conductive pad formed within a shallow trench isolation structure using a via, allowing for two-dimensional routing flexibility and reduced area requirements by avoiding interference with fin-based structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If buried conductive pads are integrated within isolation structures using fin-based transistor structures, then electrical connectivity is achieved, but routing flexibility is limited and area requirements increase
Solution Approach 1:
The patent transitions from traditional planar routing to three-dimensional routing by forming buried conductive pads that extend vertically through isolation structures and horizontally within them. This multi-dimensional approach allows signals to route through the depth of the substrate rather than being constrained to surface-level paths, thereby increasing routing flexibility while reducing the footprint area required for circuit布局.
Solution Approach 2:
The invention embeds buried conductive pads within isolation structures, effectively nesting conductive elements inside what were previously purely insulating regions. This nesting approach allows the conductive pads to occupy space within the isolation structure volume rather than requiring additional lateral space, thus reducing area requirements while maintaining electrical connectivity.
2Productivity
If feature size of semiconductor devices is decreased, then device density is improved, but space constraints in circuit layouts arise
Solution Approach 1:
By utilizing the vertical dimension through isolation structures to route signals via buried conductive pads, the invention effectively adds a third dimension to circuit layout. This allows device density to increase as features shrink, while the additional routing dimension provides extra space for signal paths without increasing the lateral footprint, thereby mitigating space constraints.
Solution Approach 2:
The invention segments the isolation structure into multiple functional regions by forming buried conductive pads at specific locations and depths. This segmentation allows different portions of the isolation structure to serve different routing functions, enabling efficient space utilization and maintaining device density while providing adequate routing space through strategic placement of conductive elements within the isolated regions.
3Adaptability or versatility
If buried conductive pads are formed within isolation structures, then routing flexibility is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates the formation of buried conductive pads into the existing isolation structure fabrication process sequence. By preparing and forming these conductive elements during the isolation structure creation steps rather than as separate post-processing operations, the manufacturing complexity is minimized while still achieving the routing flexibility benefits of three-dimensional pad placement.
Solution Approach 2:
The invention merges the formation of buried conductive pads with the isolation structure fabrication process. Instead of treating these as separate manufacturing steps, the conductive pad formation is integrated into the isolation structure creation sequence, combining multiple functions into a unified process flow that reduces overall manufacturing complexity while achieving enhanced routing flexibility.
Data Source
AI summary
A semiconductor structure includes an isolation structure formed on a substrate, a gate-all-around transistor structure formed on the isolation structure, a via electrically coupled to a gate terminal of the gate-all-around transistor structure, and a buried conductive pad formed within the isolation structure and electrically coupled to the via. The buried conductive pad can extend through the isolation structure in two dimensions, such as in both a vertical dimension and a horizontal dimension. The semiconductor structure can provide advantages in terms of routing flexibility, among other possible advantages.