Implanted Dielectric Package Structure for Warpage Reduction

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Solution Overview

Problem

Integrated circuit packages experience warpage due to material differences between components, leading to non-bond issues and circuit failures.

Innovation Solution

Implementing stress modulation dopants into dielectric layers to form stress modulation regions, which modify the warpage profile and reduce warpage, enhancing bonding consistency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple package components with different materials are bonded together to increase functionality and integration level, then the integration level and functionality are improved, but warpage occurs due to material differences

Engineering Contradiction:
Improvefunctionality and integration levelVSAvoidwarpage
Core Design Contradiction:
Adaptability or versatilityVSShape

Solution Approach 1:

The patent applies stress modulation dopants at specific locations within the dielectric layer to create localized stress regions. This allows different areas of the package to have different stress characteristics, compensating for warpage caused by material differences between bonded components while maintaining high integration levels.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent modifies the physical-chemical parameters of the dielectric layer by introducing stress modulation dopants with specific concentrations and depth profiles. This changes the stress state within the package structure, enabling warpage control without sacrificing the functionality achieved through multi-component bonding.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If warpage is reduced through stress modulation dopants, then bonding consistency is improved, but the manufacturing process complexity increases

Engineering Contradiction:
Improvebonding consistencyVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The stress modulation dopants are implanted into the dielectric layer before the bonding process. This preliminary stress modulation ensures that the package components are pre-conditioned to minimize warpage during bonding, improving bonding consistency without requiring complex real-time control during the bonding operation itself.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces mechanical warpage control methods (such as physical compression or fixture-based approaches) with a chemical/physical solution involving dopant implantation. This creates an internal stress field that passively compensates for warpage, reducing the need for complex mechanical control systems during bonding.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method improves bonding by reducing warpage and ensuring consistent fitment of package components, minimizing non-bond issues and enhancing circuit reliability.

Implementation Method 1

Implanting stress modulation dopants into dielectric layers to form stress modulation regions, which modify the warpage profile and reduce warpage

Methodology Applied
Scientific EffectStress modulation:

Data Source

PatentUS20250336687A1Packages with implantation
Publication Date: 2025.10.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250336687A1 patent drawing
  • US20250336687A1 patent drawing
  • US20250336687A1 patent drawing

AI summary

A method includes bonding a device die onto a package component. The device die includes a semiconductor substrate, and a through-via extending into the semiconductor substrate. The method further includes depositing a dielectric liner lining sidewalls of the device die, depositing a dielectric layer on the dielectric liner, and planarizing the dielectric layer and the device die. Remaining portions of the dielectric liner and the dielectric layer form a gap-filling region, and a top end of the through-via is revealed. An implantation process is performed to introduce a stress modulation dopant into at least one of the dielectric liner and the dielectric layer. A redistribution line is formed over and electrically connecting to the through-via.