Dielectric Pattern Deposition for Short-Resistant Semiconductor Gaps
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Solution Overview
Problem
As semiconductor devices become highly integrated, the narrow gaps between adjacent conductive patterns increase the risk of unintended electrical contact between vias and adjacent conductive patterns, leading to short circuits.
Innovation Solution
A method involving area-selective atomic layer deposition at 350° C. or less, using pulsing of a metal catalyst, primary and secondary purges, and controlled purge gas flow and pressure to form dielectric patterns that reduce electrical contact between vias and adjacent conductive patterns, without high-temperature processes or additional annealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature processes or additional annealing are used to form dielectric patterns, then film quality and electrical characteristics may be improved, but the process complexity and manufacturing difficulty increase
Solution Approach 1:
The patent changes the deposition temperature parameter to 350°C or less, which is lower than conventional high-temperature processes. This parameter change allows dielectric patterns to be formed with adequate electrical characteristics without requiring additional annealing processes, thus reducing process complexity while maintaining reliability
Solution Approach 2:
The patent incorporates purge gas treatment before and during the atomic layer deposition process to preliminarily prepare the surface and maintain proper deposition conditions. This preliminary action ensures that dielectric patterns form with good electrical characteristics at lower temperatures, eliminating the need for subsequent annealing steps
2Productivity
If the gap between adjacent conductive patterns is reduced to increase integration density, then the number of devices per unit area increases, but the risk of unintended electrical contact between vias and adjacent conductive patterns increases
Solution Approach 1:
The patent introduces dielectric patterns as intermediary structures between conductive patterns and vias. These dielectric patterns act as insulating barriers that prevent unintended electrical contact, allowing conductive patterns to be placed closer together without increasing short circuit risk, thus enabling higher integration density while maintaining reliability
3Device complexity
If area-selective atomic layer deposition is performed at low temperature with multiple purge steps, then dielectric patterns can be formed without additional annealing, but the deposition process time increases
Solution Approach 1:
The patent merges the dielectric pattern formation process with the atomic layer deposition process by performing area-selective deposition directly at low temperature (350°C or less). The multiple purge steps are integrated into the deposition sequence, allowing dielectric patterns to be formed in a single continuous process without separate annealing steps, thus reducing overall process time despite the complexity of multiple purge operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively forms dielectric patterns with desired film properties and electrical characteristics, reducing unintended electrical contact and maintaining excellent leakage current and breakdown field performance.
Implementation Method 1
forming second dielectric patterns on the first dielectric patterns, respectively, by an area-selective atomic layer deposition at a first temperature, wherein the first temperature may be 350° C. or less
Data Source
AI summary
A method of manufacturing a semiconductor device comprising: forming a first layer in which first conductive patterns and first dielectric patterns are alternately arranged; forming passivation layers on the first conductive patterns, respectively; and forming second dielectric patterns on the first dielectric patterns, respectively, by an area-selective atomic layer deposition at a first temperature, wherein the first temperature is 350° C. or less, wherein the area-selective atomic layer deposition includes: pulsing a metal catalyst; performing a primary purge by a purge gas; sub-pulsing a reaction precursor at least once; and performing a secondary purge by the purge gas after each of the sub-pulsing.