Self-Aligned Dielectric Spacer Liner for Contact Via Alignment
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Solution Overview
Problem
As device density increases in semiconductor manufacturing, the likelihood of unintentional electrical connections (shorts) and 'tiger tooth' conditions, which can lead to voltage breakdown failures, becomes higher due to overlay inaccuracies and the difficulty in processing thick contact etch stop layers.
Innovation Solution
A combination of a planar dielectric spacer liner with aligned openings and a self-aligned etch stop dielectric liner, using a two-step anisotropic etching process and a tri-layered interlayer dielectric (ILD) structure, is employed to mitigate bridge and tiger tooth issues in middle-end-of-the-line (MEOL) and back-end-of-the-line (BEOL) fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device density is increased to improve productivity, then productivity is improved, but manufacturing precision deteriorates due to overlay inaccuracies causing electrical shorts
Solution Approach 1:
A planar dielectric spacer liner is introduced as an intermediary layer between the first and second interlayer dielectric layers. This spacer liner includes openings that are self-aligned to the contact via structures, serving as a mediator that ensures precise alignment without requiring high overlay precision between lithography steps. The spacer liner physically guides the formation of subsequent via structures, eliminating overlay-induced misalignment.
Solution Approach 2:
The planar dielectric spacer liner is formed in advance with openings that define the precise location where subsequent via structures will be formed. By pre-establishing the alignment reference in the spacer liner before forming the contact vias and interconnect vias, the patent eliminates the need for high overlay precision during later lithography steps. The preliminary structure acts as a self-aligned template for subsequent processing.
2Reliability
If contact etch stop layer thickness is increased to improve reliability, then reliability is improved, but manufacturing precision deteriorates due to difficulty in processing thick layers causing tiger tooth conditions
Solution Approach 1:
The patent divides the single thick contact etch stop layer into multiple thinner layers: a first contact etch stop layer beneath the planar dielectric spacer liner and a second contact etch stop layer above it. This segmentation allows each layer to be processed with better etch control, avoiding the tiger tooth condition that occurs with thick single layers. The total thickness maintains the required reliability while the segmented structure enables precise manufacturing.
Solution Approach 2:
The planar dielectric spacer liner acts as an intermediary that separates the two contact etch stop layers and provides a self-aligned reference for via formation. This intermediary structure allows the etch processes to be performed with better control on thinner layers while maintaining the overall protective function against voltage breakdown. The spacer liner mediates between the two etch stop layers, enabling independent optimization of each layer's thickness.
Data Source
AI summary
A planarization dielectric layer is formed over the semiconductor device on a semiconductor substrate. A device contact via structure is formed through the planarization dielectric layer. A planar dielectric spacer liner is formed over the planarization dielectric layer, and is patterned to provide an opening over the device contact via structure. An etch stop dielectric liner and a via-level dielectric layer are formed over the planar dielectric spacer liner. An interconnect via cavity may be formed through the via-level dielectric layer by a first anisotropic etch process that may be selective to the etch stop dielectric liner, and may be subsequently extended by a second anisotropic etch process that etches the etch stop dielectric liner. An interconnect via structure may be formed in the interconnect via cavity. A bottom periphery of the interconnect via structure may be self-aligned to the opening in the planar dielectric spacer liner.