Dielectric Super-Junction Transistors for High Breakdown Voltage
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Solution Overview
Problem
High-frequency electronic devices face challenges in achieving high power density due to reduced breakdown voltage and non-uniform electric field profiles, which limit their performance in millimeter-wave and terahertz frequency regimes.
Innovation Solution
The use of high dielectric constant materials in gate barrier layers and gate-drain depletion regions to manage electric field profiles and increase charge density, enabling flat field profiles and higher breakdown voltages through dielectric super-junction field effect transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If conventional field plates are used to manage electric field distribution, then breakdown voltage is improved, but device complexity increases and gate-drain capacitance increases degrading cutoff frequency
Solution Approach 1:
A high dielectric constant material layer is introduced as an intermediary between the gate electrode and the semiconductor channel. This intermediate layer with ultra-high dielectric constant (k>25) manages the electric field distribution through its superior charge storage capability, achieving breakdown voltage enhancement without requiring complex 3-D field plate structures. The high-k material acts as a mediator that optimizes field distribution while maintaining device simplicity and reducing gate-drain capacitance compared to conventional field plate approaches.
2Speed
If operating frequency is increased to achieve millimeter-wave performance, then communication throughput is improved, but breakdown voltage decreases limiting power density
Solution Approach 1:
The dielectric constant parameter of the gate barrier layer is dramatically increased from conventional values (k<10) to ultra-high values (k>25). This parameter change fundamentally alters the electric field distribution characteristics, enabling the device to maintain high breakdown voltage even at millimeter-wave operating frequencies. The high-k material's superior charge storage capability compensates for the frequency-induced breakdown voltage reduction, allowing simultaneous achievement of high-frequency operation and high power density.
3Quantity of substance
If charge density is increased to improve current, then conduction is improved, but parallel conduction occurs in the barrier layer reducing effectiveness
Solution Approach 1:
The high dielectric constant material is strategically positioned in the gate barrier layer region where electric field management is most critical. This localized quality enhancement creates a non-uniform dielectric structure with k>25 specifically in the gate barrier region, while other device regions maintain their original properties. This local quality improvement enables high charge density accumulation in the channel without inducing parallel conduction in the barrier, as the high-k material confines and optimizes the electric field distribution precisely where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in significantly higher breakdown voltages, current densities, and power densities, along with improved RF characteristics, enabling performance beyond state-of-the-art in millimeter-wave and terahertz frequencies.
Implementation Method 1
layered structures of semiconductors and/or other materials having dielectric constants and related dielectric permittivity values that are engineered to manage electric field positions and electric field magnitudes within the devices
Implementation Method 2
A high dielectric constant gate barrier can enable high 2D electron gas charge density without parallel conduction
Data Source
AI summary
Dielectric super-junction transistors use combinations high dielectric relative permittivity materials and high-mobility materials. An associated electronic device includes a junction portion of a barrier layer adjacent a gate contact and a drain contact. A layered semiconductor device is configured with a junction dielectric permittivity that is greater than a channel dielectric permittivity in the channel layer. The junction portion has a dielectric structure that polarizes carriers within the junction portion such that excess charge on the gate is compensated by an opposite charge in the junction portion of the barrier layer proximate the gate. A sheet charge in the barrier layer is increased to form a depletion region with the channel layer that avoids a conductive parallel channel in the barrier layer to the drain contact.