Differentiable Logic Gate Networks for Trainable Binary Inference

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Solution Overview

Problem

Conventional neural networks face inefficiencies in computation and storage, particularly when using binary or Boolean parameters, leading to challenges in training and generalization, and lack the ability to perform graded predictions effectively.

Innovation Solution

A logic gate network is developed, where each neuron includes a logic operator with a probability distribution for binary inputs, enabling training via gradient descent and reducing computational complexity through sparse connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If binary or Boolean parameters are used in neural networks, then storage requirements are reduced, but gradient descent training becomes impossible due to discontinuities

Engineering Contradiction:
Improvestorage requirementsVSAvoidtrainability via gradient descent
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent changes the parameter representation from discrete binary values to continuous probability distributions. Each neuron is represented by a probability distribution over logic operators instead of fixed binary parameters, enabling continuous differentiation while maintaining the binary computation characteristic at inference time.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces probability distributions as an intermediary between the binary logic gate operations and the gradient descent optimization process. This intermediary layer allows gradients to flow continuously during training while the actual neuron operations remain binary at inference time.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If conventional neural networks use binary parameters, then computational efficiency is improved, but accuracy and generalization performance deteriorate

Engineering Contradiction:
Improvecomputational efficiencyVSAvoidaccuracy and generalization
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces dynamics by allowing the network to learn which logic operators to use through probability distributions during training, then commit to specific operators at inference time. This dynamic selection process enables the network to adapt to different tasks while maintaining efficient binary computation.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent uses partial action by training with relaxed probability distributions over multiple logic operators, then applying only the necessary operators at inference time. This allows the network to explore multiple operational modes during training while executing efficiently at inference time.

Inventive Principle:
Principle #16Partial or excessive action

3Ease of manufacture

If logic gate networks are trained with probability distributions, then trainability is improved, but computational complexity during training increases

Engineering Contradiction:
ImprovetrainabilityVSAvoidcomputational complexity during training
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent segments the training process into two distinct phases: a training phase where probability distributions are optimized using gradient descent, and an inference phase where specific logic operators are executed. This segmentation allows complex probability optimization during training while maintaining simple binary operations during inference.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20260010801A1Logic Gate Networks Generated Using Differentiable Logic Gate Models
Publication Date: 2026.01.08 UNIV KONSTANZ
  • US20260010801A1 patent drawing
  • US20260010801A1 patent drawing
  • US20260010801A1 patent drawing

AI summary

Systems and methods are described for training and deploying a logic gate neural network. In various examples, a computing system receives a training data set of input vectors with target outputs and instantiates an untrained network whose nodes are parameterized over a predefined set of potential logic operators. Training may include forward propagating a batch of input vectors, computing node outputs as differentiable functions of the potential operators, aggregating outputs by summation to form scores, evaluating a loss, and updating the differentiable parameters. A fixed network is defined after multiple iterations by selecting a single logic operator for each respective node. Examples of suitable logic operators include AND, OR, NAND, NOR, XOR, constants, inverters, direct connections, and the like. The fixed network can be implemented as an application-specific integrated circuit (ASIC) or stored in a non-transitory memory and implemented in programmable hardware, such as a field-programmable gate array (FPGA).