Differential Amplifier Common-Mode Compensation for Stable Biasing
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Solution Overview
Problem
Existing differential amplifiers face instability due to mismatched biasing currents in the differential and common mode input stages, leading to significant common mode output voltage errors and undesired current wastage, especially in low-power and low-voltage circuits.
Innovation Solution
The introduction of two capacitive elements in a multistage differential amplifier circuit allows for frequency compensation of the common mode feedback amplifier, introducing a pole and a zero in the Bode diagram without reducing the common mode feedback factor or transconductance, thus stabilizing the system without impacting the differential amplifier's performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequency compensation is applied at unit-gain frequency for the common mode feedback path, then the common mode amplifier can be stabilized, but the amplifier requires larger power consumption and silicon area due to over-design
Solution Approach 1:
The patent changes the frequency compensation parameter by applying compensation at a frequency lower than the unit-gain frequency (specifically at β times the unit-gain frequency where β is the feedback factor). This parameter change allows the common mode amplifier to achieve stability with reduced power consumption and smaller silicon area, avoiding the over-design that would result from compensating at the full unit-gain frequency.
2Reliability
If frequency compensation is applied at unit-gain frequency for the common mode feedback path, then the common mode amplifier can be stabilized, but the amplifier requires larger silicon area due to over-design
Solution Approach 1:
The patent applies frequency compensation at a reduced frequency (β times the unit-gain frequency) rather than at the full unit-gain frequency. This parameter change in the compensation frequency allows the common mode amplifier to achieve adequate stability with smaller compensation capacitors and fewer resources, thereby reducing the required silicon area while avoiding over-design.
3Reliability
If the common mode feedback amplifier is compensated at unit-gain frequency, then stability can be achieved, but the differential and common mode amplifiers require different compensation frequencies causing design complexity
Solution Approach 1:
The patent changes the compensation frequency parameter for the common mode feedback path to β times the unit-gain frequency, where β is the feedback factor of the differential path. This parameter adjustment creates a coordinated relationship between the differential and common mode compensation frequencies, allowing both amplifiers to be stabilized with a unified design approach and reducing the overall design complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution minimizes common mode output errors and current wastage, maintaining the dynamic range and power efficiency of the amplifier while ensuring stability, with only a negligible impact on the differential mode operation.
Implementation Method 1
The introduction of two capacitive elements in a multistage differential amplifier circuit allows for frequency compensation of the common mode feedback amplifier, introducing a pole and a zero in the Bode diagram
Data Source
AI summary
An amplifier includes a first input branch and a second input branch that form a differential input stage and a current mirror connected to the differential input. The current mirror is governed as a function of a common mode feedback signal applied to a control node of the current mirror. A second, amplification, stage includes a branch flowing through which is a current, which is a function of the current that flows in the first input branch, and is in turn connected to a first output branch. A capacitive element is coupled between the control node and the second stage. The circuit is symmetrical with respect to the input stage.