Differential Amplifier Programmable Circuit for Overcurrent Protection
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Solution Overview
Problem
Conventional electrical fuses can still cause adverse effects on connected devices during overcurrent events, as they may not fully halt current flow and can be damaged, leading to potential harm to nearby electrical components.
Innovation Solution
A programmable circuit with parallel paths and transistors that can be programmed to operate as either resistive or capacitive elements, allowing for controlled current flow and protection by using differential amplifier circuits and programmable FETs with ultrathin gate insulating layers, which can be switched between logic states to prevent damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional electrical fuse is used to halt current flow during overcurrent events, then current flow is interrupted, but the fuse may still cause adverse effects on connected devices and can be damaged leading to potential harm to nearby electrical components
Solution Approach 1:
The circuit is divided into two parallel paths: a first path containing a first programmable element and transistors, and a second path containing a second programmable element and transistors. This segmentation allows the circuit to selectively activate different protection mechanisms based on the overcurrent event characteristics, improving protection reliability while minimizing adverse effects on connected devices.
Solution Approach 2:
The programmable elements (programmable FETs) can be dynamically reconfigured between different operational states (resistive or capacitive) through programming. This dynamic adaptability allows the protection circuit to respond optimally to different overcurrent scenarios, enhancing protection effectiveness while reducing harmful effects on connected equipment.
2Ease of manufacture
If traditional current-based programming methods are used, then programming is simple, but the risk of overheating or component damage increases
Solution Approach 1:
The patent replaces traditional current-based programming with voltage-based programming using ultrathin gate insulating layers. This substitution allows programming to be performed by applying specific voltages that create controlled breakdown in the gate insulator, forming a conductive path without generating excessive heat. This method maintains programming simplicity while eliminating the overheating and component damage risks associated with current-based methods.
Solution Approach 2:
The patent changes the programming parameter from current to voltage. By applying high voltage pulses to the gate electrode of programmable FETs with ultrathin gate insulating layers, the circuit achieves programming through controlled dielectric breakdown. This parameter change enables programming without the thermal effects that cause overheating and component damage in traditional current-based methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The programmable circuit effectively manages current flow, preventing damage to connected devices by allowing for controlled switching and maintaining constant output values, enhancing reliability and reducing the risk of overheating or component damage compared to traditional current-based programming methods.
Implementation Method 1
programmable FETs with ultrathin gate insulating layers, which can be switched between logic states
Data Source
AI summary
Provided is a programmable circuit. The programmable circuit includes a first path and a second path connected in parallel between a first voltage node and a second voltage node. The first path includes a first programmable element, a first node, a first pull-up transistor, a second node, and a first pull-down transistor connected in series between the first voltage node and the second voltage node. The second path includes a second programmable element, a third node, a second pull-up transistor, a fourth node, and a second pull-down transistor connected in series between the first and second voltage nodes. A gate electrode of the first pull-up transistor, a gate electrode of the first pull-down transistor, and the fourth node are electrically connected to one another. A gate electrode of the second pull-up transistor, a gate electrode of the second pull-down transistor, and the second node are electrically connected to one another.