Differential Delay Circuit for Stable PUF Bit Generation
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Solution Overview
Problem
Existing silicon-chip-based PUFs face challenges with poor bit stability and statistical quality due to process variations, making them vulnerable to attacks and requiring costly error correction, especially in delay-based PUFs like ring oscillators and arbiter PUFs.
Innovation Solution
The introduction of highly sensitive delay elements with adjustable stability to ambient variations, combined with switchable delay elements and differential feedback transfer gates, enhances bit stability and statistical quality, allowing for effective preselection of stable PUF bits and improved resistance to physical attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay-based PUFs (ring oscillators, arbiter PUFs) are used, then PUF functionality is achieved, but bit stability and statistical quality deteriorate due to process variations
Solution Approach 1:
The PUF circuit is divided into multiple independent delay paths with process variation compensation units. Each path processes signals independently through parallel delay elements, and the compensation units separately correct variations in each path. This segmentation allows individual optimization of each path's stability while maintaining overall statistical quality, resolving the contradiction between bit stability and manufacturing precision.
Solution Approach 2:
The patent introduces process variation compensation units that dynamically adjust delay parameters based on detected variations. By changing the delay parameters adaptively to compensate for process variations, the system maintains high bit stability without sacrificing statistical quality. The compensation units modify timing parameters in real-time to counteract manufacturing variations, thus resolving the contradiction between reliability and manufacturing precision.
2Reliability
If process variation compensation is implemented, then bit stability improves, but device complexity increases
Solution Approach 1:
Process variation compensation units are introduced as intermediary components between the delay paths and the PUF evaluation logic. These units act as mediators that detect variations and apply corrections without requiring complete redesign of the entire PUF circuit. By placing compensation units at strategic intermediate points, the patent achieves bit stability improvement with minimal added complexity, as the intermediaries handle variation compensation locally rather than requiring system-wide complexity increases.
Solution Approach 2:
The compensation units perform preliminary correction of process variations before the signals reach the PUF evaluation stage. By pre-compensating for variations in the delay paths, the main PUF logic can operate with simpler, more reliable bit stability without requiring complex post-processing. This preliminary action approach reduces overall circuit complexity by handling variations early in the signal path, preventing complexity from propagating through the entire system.
3Manufacturing precision
If multiple delay paths are used, then statistical quality improves, but susceptibility to physical attacks worsens
Solution Approach 1:
The patent introduces asymmetric process variation compensation mechanisms that treat different delay paths differently. Rather than uniform compensation, each path receives tailored compensation based on its specific characteristics and threat profile. This asymmetry makes it difficult for attackers to apply uniform physical attack methods across multiple paths, as each path has unique compensation parameters and variation profiles. The asymmetric design maintains statistical quality through multiple paths while reducing susceptibility to physical attacks by preventing attackers from exploiting common patterns across paths.
Data Source
AI summary
A delay circuit includes an electronic transmission element with a first input and a first output. The first input is coupled to the first output by two first switches wired in parallel. The first switches each have a control input, a second input and a second output. The second input is coupled to the second output by two second switches wired in parallel. The circuit further includes an input circuit to receive an input signal and feed the input signal to one of the transmission element inputs and feed the inverted input signal to the other of the transmission element inputs, and an output circuit. The output circuit is configured such that the output signal only changes in the case of a change in the input signal if the change in the input signal has brought about a change both at the first output and at the second output.