Differential Memory Clock Calibration for Accurate BIST Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory systems face challenges in maintaining accurate clock signals due to duty cycle deviations, which can lead to incorrect operations and require costly Automatic Test Equipment (ATE) for testing, increasing costs and reducing test accuracy.
Innovation Solution
Incorporating a clock generation circuit that generates differential oscillation signals with adjustable duty cycles within preset ranges, allowing for Built-In Self Test (BIST) capabilities and reducing dependence on external test equipment by using high-frequency signals to test internal circuits, thereby monitoring and adjusting duty cycles to ensure accurate operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external test equipment (ATE) is used to test clock signals, then test accuracy can be maintained, but system cost increases and self-testing capability is reduced
Solution Approach 1:
The patent implements a clock duty cycle calibration circuit that enables the memory device to automatically test and calibrate its own clock signals without external equipment. The circuit generates test clock signals, monitors duty cycle deviations, and performs self-calibration, eliminating dependence on expensive Automatic Test Equipment (ATE) while maintaining measurement accuracy.
Solution Approach 2:
The clock generation circuit is designed to perform multiple functions: generating operational clock signals for normal memory operations and generating test clock signals for self-diagnosis and calibration. This multi-functionality allows the same circuit to serve both operational and testing purposes, reducing the need for separate external test equipment.
2Reliability
If duty cycle deviations are not monitored and adjusted, then circuit operation may become incorrect, but adding monitoring increases device complexity
Solution Approach 1:
The patent implements a feedback mechanism where the clock duty cycle calibration circuit continuously monitors the duty cycle of generated clock signals and automatically adjusts calibration parameters when deviations are detected. This closed-loop feedback ensures reliable operation by correcting duty cycle errors without requiring complex external monitoring systems.
Solution Approach 2:
The calibration circuit acts as an intermediary between the clock generation circuit and the rest of the memory system. It introduces minimal additional complexity by inserting a calibration layer that mediates between clock signal generation and consumption, ensuring accurate timing without significantly increasing overall circuit complexity.
3Measurement precision
If high-frequency signals are used for internal testing, then test accuracy improves and external equipment is reduced, but power consumption increases
Solution Approach 1:
The clock duty cycle calibration circuit performs high-frequency signal generation and testing periodically rather than continuously. It conducts self-tests at scheduled intervals to check clock signal integrity and performs calibration when needed, rather than constantly operating at high frequency. This periodic operation maintains test accuracy while significantly reducing average power consumption compared to continuous high-frequency operation.
Data Source
AI summary
A memory includes: a clock generation circuit, configured to generate a first oscillation signal and a second oscillation signal. The first oscillation signal and the second oscillation signal have a same frequency but opposite phases, and a duty cycle of the first oscillation signal and a duty cycle of the second oscillation signal are both within a first preset range. The memory further includes a differential input circuit, which is configured to receive a first external signal and a second external signal, and generate a first internal signal and a second internal signal. The clock generation circuit is configured to monitor the duty cycle of the first internal signal or the duty cycle of the second internal signal, and enable the duty cycle of the first internal signal or the duty cycle of the second internal signal to be within a second preset range.