Differential Polysilicon Doping for CMOS Transistor Stability
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Solution Overview
Problem
CMOS integrated circuits face performance degradation due to increased TOXINV (transconductance loss) in PMOS load transistors caused by n-type dopant cross-diffusion from NMOS polysilicon, leading to variability in transistor performance and stability issues, especially in SRAMs, as design rules shrink and pre-etch n-poly mask edge spacing tightens.
Innovation Solution
A method of fabricating CMOS integrated circuits with differential polysilicon doping by masking portions of the polysilicon layer to prevent pre-gate etch implant in specific regions, allowing higher dopant doses in unmasked areas, and using rapid thermal annealing to activate dopants, thereby reducing cross-diffusion and enhancing transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pre-etch n-poly mask edge spacing is tightened to improve circuit density, then manufacturing precision is improved, but dopant cross-diffusion control becomes more difficult leading to increased TOXINV variability
Solution Approach 1:
The patent uses local quality to maintain different doping characteristics in different spatial regions despite tight design rules. By locally protecting PMOS regions from n-type dopant implantation while allowing NMOS regions to receive full doping, the invention enables tight mask edge spacing without compromising transistor performance stability. Each region's quality is optimized independently, resolving the contradiction between scaling precision and performance stability.
2Quantity of substance
If higher dopant doses are used in polysilicon to reduce TOXINV, then inversion charge density is improved, but cross-diffusion effects increase causing variability in transistor characteristics
Solution Approach 1:
The patent segments the dopant distribution to achieve high inversion charge density only where needed. By dividing the polysilicon structure into regions that require high doping (NMOS gates) and regions that require low doping (PMOS gates), the invention enables higher overall dopant doses without increasing cross-diffusion variability. The segmented approach ensures that high dopant concentrations benefit only the intended transistor type, maintaining characteristic consistency across the circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves NMOS transistor performance, reduces TOXINV, and maintains stability in SRAMs by blocking pre-gate n+ poly implants in memory cells, allowing tighter design rules and improved scaling without degrading non-memory NMOS transistor performance.
Implementation Method 1
n-type dopant (e.g. P or As) is implanted into the polysilicon layer corresponding to the NMOS gate area
Implementation Method 2
An optional dopant anneal may follow the n+ poly pre-gate etch implant to activate the dopant
Data Source
AI summary
A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and pre-gate etch implant of a first dopant type into an unmasked portion of the polysilicon layer is performed, wherein masked portions of the polysilicon layer are protected from the first dopant. The polysilicon layer is patterned to form a plurality of polysilicon gates and a plurality of polysilicon lines, wherein the masked portion includes at least one of the polysilicon lines which couple a polysilicon gate of a PMOS device to a polysilicon gate of an NMOS device. Fabrication of the integrated circuit is then completed, wherein the integrated circuit includes at least one first region formed in the masked portion lacking the first dopant in the polysilicon gates from the pre-gate etch implant and at least one second region formed in the unmasked portion having the first dopant in the polysilicon gates from the pre-gate etch implant.