Differential Signal Source Circuit for Low Phase Noise GSM Clocks
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Solution Overview
Problem
Current GSM signal source devices face challenges in achieving low phase noise, particularly at 20 MHz offset, due to limitations in CMOS technology such as low-quality on-chip inductors and increased 1/f noise, which affect compliance with GSM specifications.
Innovation Solution
The signal source device employs a cascaded configuration of latch units, an inverter unit, and a voltage-shifting unit, along with frequency dividers, to generate differential oscillating signals and shift voltage levels, thereby reducing phase noise through improved inductor quality and amplitude enhancement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If CMOS technology is used for signal source device, then integration and miniaturization are improved, but phase noise performance deteriorates due to low-quality on-chip inductors and increased 1/f noise
Solution Approach 1:
The patent changes the operating parameters by using a differential oscillator architecture instead of single-ended, and employs voltage-shifting techniques to optimize the signal levels. This transforms the phase noise characteristics without requiring external components, maintaining CMOS integration while improving phase noise performance
Solution Approach 2:
The patent combines multiple circuit techniques within the CMOS device: differential signaling, voltage-shifting units, and cascaded latch units work together as a composite solution. This integrated approach leverages the strengths of each technique to achieve low phase noise while maintaining on-chip integration
2Productivity
If channel scale-down is implemented, then transistor density is improved, but 1/f noise increases affecting phase noise
Solution Approach 1:
The patent extracts and eliminates the problematic 1/f noise components through differential signaling architecture. By using complementary transistors in a differential configuration, the low-frequency noise from scaled transistors is rejected, allowing channel scale-down to proceed while maintaining phase noise performance
3Device complexity
If single CMOS chip solution is used, then device integration is improved, but inductor quality deteriorates leading to higher phase noise
Solution Approach 1:
The patent replaces the mechanical/physical inductor-based oscillation approach with an electronic solution using voltage-shifting units and differential latches. This substitution eliminates the need for high-quality on-chip inductors, allowing standard CMOS fabrication processes to be used while achieving the required phase noise performance
Data Source
AI summary
A signal source device is provided and includes a plurality of latch units, an inverter unit, and a voltage-shifting unit, which may include a capacitance unit. The plurality of latch units are substantially cascaded. The inverter unit is coupled to the latch units. The voltage-shifting unit has a first terminal coupled to the inverter unit and one of the latch units and a second terminal receiving a first input signal, for shifting a voltage level at the first terminal according to the first input signal.