Digital-Analog Memory Integrated Deep Learning Accelerator
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Solution Overview
Problem
Existing deep learning accelerators face challenges in achieving high computation speed and energy efficiency, particularly when implementing artificial neural networks on devices with low precision digital methods.
Innovation Solution
A digital-analog memory integrated deep learning accelerator system is proposed, which combines digital and analog arrays to perform matrix-level learning. The system includes a main digital element for storing weights, an analog element for updating and storing gradient information, and a sub-digital element for transferring values exceeding a threshold to the main digital element.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a deep learning accelerator is implemented using only digital methods, then calculation accuracy is maintained, but calculation speed becomes slower and area occupied increases as the array grows larger
Solution Approach 1:
The system divides the deep learning accelerator into two separate arrays: a first array implemented in digital methods for maintaining calculation accuracy, and a second array implemented in analog methods for achieving high-speed parallel computation. This segmentation allows each array to operate in its optimal domain without compromising overall system performance.
Solution Approach 2:
The patent combines digital and analog computing arrays into a unified deep learning accelerator system. The digital array ensures precision for weight storage and critical computations, while the analog array provides high-speed parallel processing for matrix operations, achieving both accuracy and speed simultaneously.
2Productivity
If a deep learning accelerator is implemented using only analog methods, then high computation speed and energy efficiency are achieved, but precision and reliability deteriorate
Solution Approach 1:
The system separates computation tasks between analog and digital domains. The analog array handles high-speed parallel matrix operations where absolute precision is less critical, while the digital array handles precision-sensitive operations such as weight storage and activation functions, ensuring overall calculation accuracy.
Solution Approach 2:
A conversion interface is introduced between the analog and digital arrays to translate analog computation results into digital form. This intermediary ensures that precision requirements are met by converting analog signals back to digital domain where precision can be maintained, bridging the gap between speed and accuracy.
3Power
If the array size is increased to improve computation capacity, then processing power increases, but calculation speed decreases and area occupied increases in digital accelerators
Solution Approach 1:
The system merges digital and analog array architectures to achieve high processing power without sacrificing calculation speed. The analog array's inherent parallel processing capability allows large-scale matrix operations to be performed simultaneously, maintaining high computation speed even as processing power increases through array expansion.
Solution Approach 2:
The patent changes the implementation parameter of the array from purely digital to a hybrid digital-analog architecture. This parameter change enables the system to leverage the analog domain's superior parallel processing capabilities for large arrays, maintaining calculation speed while increasing processing power through array expansion.
Data Source
AI summary
A digital-analog memory integrated deep learning accelerator system may include: a main digital device including a first array, the first array having digital circuits and configured to store weights for on-chip learning; an analog device including a second array, the second array having analog circuits and configured to update and store gradient information about the weights during the on-chip learning; and a sub-digital device including a third array, the third array having digital circuits and configured to store values read from the second array and to transfer a value exceeding a threshold to the first array. The digital-analog memory integrated deep learning accelerator system may perform a matrix-level learning process through an array set including the first array, the second array, and the third array. An artificial neural network learning method for a digital-analog memory integrated deep learning accelerator system is also disclosed.