Digital Camouflage Circuit Using Threshold-Skewed Inverter Chains
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Solution Overview
Problem
Conventional camouflage circuits for semiconductor devices are manually intensive and costly, requiring significant work and risk to ensure sufficient insertion without affecting the original circuit design's functionality, as they are typically inserted at the netlist stage after synthesis.
Innovation Solution
All-digital camouflage circuits that utilize standard cell libraries with different transistor threshold options (LVT, RVT, HVT) to create timing skew differences, allowing for insertion before the synthesis stage without disrupting the normal RTL design flow, making them easier to integrate and reducing manual intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional camouflage circuits are inserted at the netlist stage after synthesis, then the circuit functionality can be protected, but the manual insertion process creates significant work and risk affecting the original circuit design
Solution Approach 1:
The patent applies preliminary action by inserting camouflage circuit templates at the RTL design stage rather than at the netlist stage after synthesis. This early insertion allows the camouflage circuits to be automatically synthesized along with the original circuit, eliminating manual intervention and reducing the risk of affecting circuit functionality while still achieving the protection goal
2Reliability
If conventional camouflage circuits are manually inserted, then circuit protection is achieved, but the process is time-consuming and costly
Solution Approach 1:
The patent implements self-service by enabling the synthesis tool to automatically handle the insertion and synthesis of camouflage circuits from RTL descriptions. The system uses automated template instantiation and parameter binding, allowing the design process to serve itself without manual engineering intervention, thereby significantly reducing time and cost while maintaining protection effectiveness
3Extent of automation
If camouflage circuits are inserted early in the design flow, then automation is improved, but the risk of affecting original circuit functionality increases
Solution Approach 1:
The patent applies copying by using template-based camouflage circuit designs that are pre-validated to be functionally equivalent to standard cells. These templates are copied and instantiated with bound parameters during automatic synthesis, ensuring that the camouflage circuits replicate standard cell behavior exactly, thus maintaining original circuit functionality while achieving automation
Data Source
AI summary
Described are technologies of all-digital camouflage circuits. The camouflage circuit can include a first chain of inverters, synthesized with a first standard cell with a first transistor threshold, and a second chain of inverters, synthesized with a second standard cell with a second transistor threshold that is different than the first transistor threshold. A first flip-flop receives a first output of the first chain as a data input and a second output of the second chain as a clock input. A second flip-flop receives the second output as a data input and the first output of the first chain as a clock input. Given the different transistor thresholds, one flip-flop always outputs an active signal that corresponds to an input signal applied to the first chain and the second chain. The other flip-flop always output a constant signal, such an always low signal.