Digital Circuit Verification Monitor Using Free Variables
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Solution Overview
Problem
Current methods for formal verification of digital circuits lack a reliable way to determine the progress and completeness of the verification process, especially at the Register Transfer Level (RTL) description, requiring significant computational resources and being limited to synthesized hardware designs.
Innovation Solution
A method that uses free variables to assess the validity of formal properties in digital circuit representations, allowing for the determination of covered and uncovered statements, and indicating the progress of the verification process without the need for error models or synthesis, enabling analysis directly at the RTL level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If formal verification is performed on RTL description using conventional methods, then verification completeness can be assessed, but it requires significant computational resources and time
Solution Approach 1:
The patent extracts and replaces specific input values with free variables in the RTL description, allowing the verification system to assess coverage without exhaustively testing all possible input combinations. This selective extraction of critical verification points enables comprehensive assessment with reduced computational effort.
Solution Approach 2:
The patent performs preliminary substitution of input values with free variables before the main verification process. This preliminary action prepares the RTL description in a form that enables efficient coverage assessment, avoiding the need for time-consuming exhaustive testing during the actual verification.
2Measurement precision
If conventional verification methods are used, then coverage can be determined, but the method is limited to synthesized hardware designs and cannot be applied at RTL level
Solution Approach 1:
The patent creates a universal verification method that works across multiple design stages. By using free variable substitution directly on RTL descriptions rather than requiring synthesized hardware, the method becomes adaptable to both RTL level and post-synthesis stages, eliminating the limitation of conventional methods.
Solution Approach 2:
The patent introduces free variables as an intermediary mechanism between the RTL description and the verification process. These free variables act as a bridge that enables coverage assessment at the RTL level without requiring translation to synthesized hardware, thus extending applicability while maintaining measurement precision.
3Reliability
If exhaustive input testing is performed to ensure complete verification, then all bugs can be detected, but computational costs and time increase significantly
Solution Approach 1:
The patent applies partial action by substituting only critical input values with free variables rather than performing exhaustive testing of all possible inputs. This selective approach maintains sufficient bug detection capability while significantly reducing computational costs and energy consumption.
Solution Approach 2:
The patent replaces the mechanical exhaustive testing process with a more efficient free variable substitution mechanism. Instead of systematically testing every possible input combination (mechanical approach), the system uses symbolic substitution and logical reasoning to assess coverage, reducing computational burden while maintaining reliability.
Data Source
AI summary
A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.