Digital Clock Generation with Programmable Duty Cycle Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional digital clock generation apparatuses based on programmable delay element chains are limited in generating various duty cycles and frequency clocks, leading to increased hardware complexity and difficulty in controlling duty cycles, especially in applications requiring precise 50% duty cycle clocks.
Innovation Solution
A digital clock generation apparatus comprising a delayed clock generation unit, a selection unit, a multiplied clock generation unit, a phase separation unit, and a duty cycle processing unit, which generates multiple delayed clock signals, multiplies clock frequencies, separates phases, and produces duty cycle clocks with preset intervals and cycles, simplifying hardware and improving control over duty cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional PDEC-based digital clock generation apparatus generates only 1× single-phase or multi-phase clocks, then the hardware structure is simple, but the adaptability to applications requiring various clocks is poor and the number of delay configuration chains increases
Solution Approach 1:
The patent implements dynamic frequency multiplication by using a phase-locked loop (PLL) circuit that can dynamically adjust the multiplication ratio (N) based on control signals. The PLL dynamically adjusts the output clock frequency by changing the division ratio in the feedback path, allowing the system to generate various frequency clocks (n× clocks) without adding multiple fixed delay chains, thus resolving the contradiction between versatility and device complexity
Solution Approach 2:
The patent changes the operational parameters of the clock generation system by introducing programmable delay elements that can be configured to introduce different delay amounts. This allows the same hardware structure to generate different phase shifts and frequency multiplications by changing the delay parameter, enabling various clock generation modes without increasing hardware complexity
2Ease of operation
If a conventional PDEC-based digital clock generation apparatus is used, then the hardware is simple, but the control over duty cycles is difficult and accurate 50% duty cycle generation is limited
Solution Approach 1:
The patent introduces a duty cycle adjustment circuit as an intermediary component between the phase splitter and the output stage. This circuit receives the split-phase clock signals and uses programmable delay elements to independently adjust the duty cycle of each phase, enabling precise 50% duty cycle generation and easy control without modifying the core PDEC structure
Solution Approach 2:
The patent segments the clock generation process into independent functional blocks: delay chain, phase splitter, and duty cycle adjustment circuit. This segmentation allows each block to be optimized independently, with the duty cycle adjustment circuit specifically designed to provide precise 50% duty cycle control, resolving the contradiction between ease of operation and manufacturing precision
3Adaptability or versatility
If multiple delay configuration chains are added to generate 180° delayed clock signal, then the clock generation capability is improved, but the amount of hardware increases and control becomes more difficult
Solution Approach 1:
The patent makes the single delay configuration chain universal by making it programmable and configurable to generate different delay amounts. The same delay chain can be configured to produce 180° phase shift, other phase shifts, or frequency multiplication ratios by changing the control signals, eliminating the need for multiple dedicated delay chains and reducing hardware complexity while maintaining versatility
Data Source
AI summary
The present invention relates to a digital clock generation apparatus. The digital clock generation apparatus is directed to providing a digital clock generation apparatus in which hardware is simple, duty cycles are easily controlled, and various duty cycles and various frequency clocks (n× clocks) are provided as compared to a 1× single-phase clock generation apparatus or a 1× multi-phase clock generation apparatus based on the conventional programmable delay element chain.