Digital Clock Recovery With Adaptive Quantization for Jitter Control
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Solution Overview
Problem
High data rates in communication receivers lead to channel quality degradation due to intersymbol interference and noise, making it challenging to achieve reliable clock and data recovery, especially with varying temperature and voltage conditions affecting analog CDRs, and digital CDRs struggling to meet jitter requirements.
Innovation Solution
A clock and data recovery device comprising a phase detector, quantizer, and loop filter, with a sinusoidal jitter frequency band detector and programmable look-up table to adjust gains and thresholds, enabling all-digital CDR designs that can handle sinusoidal jitter and tailor performance to specific requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog CDR implementations adjust component values to meet jitter requirements, then jitter performance is improved, but manufacturing precision deteriorates due to process variations and temperature dependence
Solution Approach 1:
The patent replaces analog CDR circuitry with a fully digital CDR implementation. The phase detector, quantizer, and loop filter are implemented using digital logic circuits instead of analog components. This substitution eliminates the dependence on temperature-sensitive analog components (resistors, capacitors, current sources) and their manufacturing variations, while maintaining the ability to meet jitter requirements through digital processing and programmable parameters.
2Manufacturing precision
If digital CDR solutions are used to avoid analog shortcomings, then manufacturing precision is improved, but jitter performance deteriorates at high data rates
Solution Approach 1:
The patent implements a dynamic quantizer that adapts its thresholds based on the detected jitter frequency band. The system uses a sinusoidal jitter frequency band detector to identify the jitter characteristics and dynamically adjusts the quantizer thresholds and loop filter gains accordingly. This dynamic adaptation enables the digital CDR to optimize its performance for different jitter conditions, resolving the issue of fixed digital CDRs failing to meet jitter requirements at high data rates.
Solution Approach 2:
The patent changes the operating parameters of the quantizer and loop filter based on the detected jitter characteristics. Specifically, the quantizer thresholds and loop filter gains are adjusted as functions of the detected jitter frequency band. This parameter adaptation allows the digital CDR to achieve the necessary jitter performance by optimizing its response to different types of jitter encountered at high data rates.
3Device complexity
If fixed threshold quantizers are used in digital CDR, then device complexity is reduced, but adaptability deteriorates under varying temperature and voltage conditions
Solution Approach 1:
The patent implements a self-adjusting quantizer that automatically adapts its thresholds based on the detected jitter frequency band. The system uses the output of the sinusoidal jitter frequency band detector to dynamically set the quantizer thresholds, eliminating the need for external manual calibration or complex temperature compensation circuits. This self-service mechanism provides environmental adaptability while maintaining relatively simple device structure.
Data Source
AI summary
A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples or the phase error samples to control the phase-controlled clock. A frequency detector, determining the frequency of jitter present in the input data signal, addresses a look-up table to provide the jitter-frequency dependent high and low threshold values and to control which phase error samples is processed by the loop filter. The frequency detector determines the jitter frequency by taking the ratio of peak values of low pass-filtered phase error samples.