Digital Delay Estimation Using DCDL and TDC Fast Locking
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Solution Overview
Problem
Conventional delay locked loops (DLLs) require a large number of time-to-digital converter (TDC) stages to achieve large delay resolution, leading to increased layout area and power consumption, as well as reduced linearity, especially in high-speed applications.
Innovation Solution
A delay estimation device comprising a pulse generator, a digitally controlled delay line (DCDL), a TDC, and a control circuit that operates in a fast lock mode to reduce the number of TDC stages needed by using a combination of delay line codes to estimate delay, allowing for a more efficient locking process with improved linearity and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional DLL increases/counts delay from minimum to desired value, then delay accuracy is improved, but locking time increases significantly
Solution Approach 1:
The patent applies preliminary action by using a time-to-digital converter (TDC) to pre-measure the timing difference between the reference clock signal and divided clock signal before the main delay locking process. This preliminary measurement provides an initial estimate of the required delay, allowing the DLL to start from a closer point to the final target rather than from minimum delay, thereby significantly reducing the number of counting cycles needed for locking while maintaining delay accuracy.
2Loss of time
If TDC stages are increased to reduce lock time, then locking speed is improved, but layout area and power consumption increase
Solution Approach 1:
The patent uses a simplified timing measurement approach where the TDC captures timing information in a compact form (timing code stored in D flip-flops) rather than using multiple complex TDC stages. The timing difference is converted to a digital code that represents the delay estimate, allowing the system to achieve fast locking with minimal hardware overhead instead of scaling up the number of TDC stages.
Solution Approach 2:
The patent extracts only the essential timing information needed for delay estimation using a minimal TDC structure. Instead of using multiple TDC stages to cover the entire delay range, the system extracts the timing difference between clock edges and converts it to a digital code, taking out only the necessary measurement function with reduced hardware complexity and area.
3Measurement precision
If more TDC stages are added to handle larger desired delay, then delay range is improved, but power consumption increases
Solution Approach 1:
The patent changes the measurement parameter from analog delay time to a digital timing code representation. By converting the timing difference to a digital code in the TDC, the system can represent large delay ranges using minimal bits rather than requiring proportional increases in TDC stages. This parameter transformation allows large detection ranges to be achieved with constant power consumption regardless of the delay magnitude.
4Measurement precision
If conventional DLL structure is used with large desired delay, then delay accuracy is maintained, but linearity deteriorates
Solution Approach 1:
The patent replaces the mechanical counting-based delay measurement with a digital timing code measurement system. Instead of mechanically counting delay cycles from minimum to desired value, the TDC captures the timing difference directly and converts it to a digital code, eliminating the cumulative errors and non-linearities associated with iterative counting methods. This substitution maintains delay accuracy while improving linearity across the entire delay range.
Data Source
AI summary
The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.