Digital DLL Skew Correction With Training-Phase Power Saving
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Solution Overview
Problem
Existing data reception devices face challenges in correcting signal skew while minimizing power consumption, particularly in source-synchronous systems like MIPI DPHY, where power consumption is high due to skew correction processes.
Innovation Solution
A low-power digital delay-locked loop (DLL) with a skew correction function is implemented, utilizing a reference clock generation unit and data sampling unit, which includes digitally-controlled delay lines and phase detection circuits, allowing for efficient skew correction by adjusting delay values and selectively powering down components to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay-locked loop (DLL) is used for skew correction in source-synchronous systems, then skew correction capability is achieved, but power consumption increases
Solution Approach 1:
The patent performs skew correction in advance during a training phase before normal data transmission. The DLL measures and corrects skew values preliminarily, then uses these pre-determined values during normal operation, avoiding continuous high-power DLL operation and thus reducing overall power consumption while maintaining skew correction capability
Solution Approach 2:
The DLL operates periodically rather than continuously - it is activated during training phases to perform skew correction, then powered down or placed in low-power mode during normal data transmission. This periodic operation pattern maintains the necessary skew correction functionality while significantly reducing average power consumption
2Stability of the object's composition
If independent clocks are generated through local oscillators for each lane, then clock synchronization is achieved, but circuit area and complexity increase
Solution Approach 1:
The patent merges the clock generation function into a single shared source-synchronous clock system rather than using separate local oscillators for each lane. All lanes share the same clock source, which is distributed through the system, thereby achieving clock synchronization across lanes while significantly reducing the total circuit area and complexity compared to independent oscillators
Solution Approach 2:
The single clock source serves multiple lanes universally, providing clock signals to all data lanes simultaneously. This universal clock distribution approach achieves synchronization across all lanes without requiring dedicated oscillators for each lane, reducing overall circuit area while maintaining synchronization stability
Data Source
AI summary
A data reception device includes a reference clock generation unit including a first DCDL, a phase detection circuit, and a digital loop filter, and receiving an input clock signal CK0 and outputting the input clock signal and a first phase clock signal CK90 having a phase difference of 90 degrees with respect to the input clock signal; and a data sampling unit including a second DCDL that receives a data signal DI, the input clock signal, and the first phase clock signal, and delays the data signal, and sampling and outputting a data value of the data signal at an edge of the input clock signal, thereby remarkably reducing an amount of power consumption used for skew correction.