Digitally Controlled FLL for Low-Power Low-Frequency Clocking

Solution Overview

Problem

Existing clock generation technologies, particularly in portable wireless devices, face inefficiencies with low-frequency and high-jitter clocks, leading to power wastage and larger design areas due to the use of phase-locked loops (PLLs), which are not suitable for devices requiring low power and compact designs.

Innovation Solution

A frequency-locked loop (FLL) system utilizing a digitally controlled oscillator (DCO) that selectively stops oscillation after a time period, allowing the oscillator to remain in an active mode and adjust control settings to maintain a low-frequency output clock with high jitter, thereby reducing power consumption and design area, and enabling sharing of power supplies with other devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a phase-locked loop (PLL) circuit is used to generate low-frequency clocks, then clock generation capability is improved, but power consumption increases and design area increases

Engineering Contradiction:

Improveclock generation capabilityVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent extracts the essential frequency multiplication function from the complete PLL circuit, implementing only a frequency-locked loop (FLL) that uses a digitally controlled oscillator (DCO) and counter-based frequency detection. This removes the phase detection and correction mechanisms of traditional PLLs, significantly reducing power consumption while maintaining the ability to generate low-frequency clocks with high jitter tolerance.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent employs a digitally controlled oscillator (DCO) with simple digital logic control instead of complex analog PLL components. The DCO can be rapidly reconfigured through digital control signals, allowing the system to adapt to different frequency requirements without requiring complex analog circuitry, thereby reducing both power consumption and design area.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

2Productivity

If a phase-locked loop (PLL) circuit is used to generate low-frequency clocks, then clock generation capability is improved, but design area increases

Engineering Contradiction:

Improveclock generation capabilityVSAvoiddesign area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The patent extracts the essential frequency multiplication function from the complete PLL circuit, implementing only a frequency-locked loop (FLL) that uses a digitally controlled oscillator (DCO) and counter-based frequency detection. This removes the phase detection and correction mechanisms of traditional PLLs, significantly reducing power consumption while maintaining the ability to generate low-frequency clocks with high jitter tolerance.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces complex analog PLL circuitry with a digital implementation using a digitally controlled oscillator (DCO) and counter-based frequency detection. The DCO is controlled by digital logic that counts output clock cycles and adjusts the oscillator frequency accordingly, substituting mechanical/analog phase-locked mechanisms with digital frequency counting and control.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If oscillation is continuously maintained to ensure clock availability, then clock reliability is improved, but power consumption increases

Engineering Contradiction:

Improveclock availabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements periodic oscillation control where the DCO is activated only when frequency adjustment is needed. The control logic determines when the oscillator should be active based on frequency requirements, allowing the system to enter low-power states when continuous clock generation is not necessary, thereby reducing overall power consumption while maintaining reliability when needed.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS8994458B2Oscillator based frequency locked loop

Publication Date: 2015.03.31 QUALCOMM INC

AI summary

A method includes determining a control setting and selectively stopping oscillation of an oscillator after a time period. The oscillator is configured to remain in an active mode after the time period. The method further includes applying the control setting to the oscillator.