Digitally Controlled Frequency Multiplier for Low-Noise mmWave LO Generation

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Solution Overview

Problem

Existing frequency multiplier technologies face inefficiencies in generating high-frequency Local Oscillator (LO) signals, such as high power consumption, large die-area, and phase noise issues, particularly in mmWave frequency bands, which are challenging for radar and wireless communication devices.

Innovation Solution

A digitally-controlled frequency multiplier (DCM) is employed to generate high-frequency LO signals efficiently, utilizing a digitally-controlled oscillator (DCO) to overcome the limitations of direct LO generation techniques and multi-stage doubler/tripler multipliers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If direct LO generation techniques are used, then the circuit complexity is reduced, but the power consumption increases and phase noise performance deteriorates

Engineering Contradiction:
Improvecircuit complexityVSAvoidpower consumption
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

The frequency multiplication function is divided into multiple stages: a first frequency multiplier stage and a second frequency multiplier stage. Each stage handles a portion of the total multiplication factor, allowing optimization of each stage independently for lower power consumption while maintaining overall system functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An intermediate frequency signal is introduced between the first and second frequency multiplier stages. This intermediate signal serves as a mediator that allows the system to achieve high frequency multiplication through staged processing rather than a single high-power stage, reducing overall power consumption and improving phase noise performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If multi-stage doubler/tripler multipliers are used, then the frequency multiplication capability is improved, but the die-area increases

Engineering Contradiction:
Improvefrequency multiplication capabilityVSAvoiddie-area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The frequency multiplier apparatus is designed to handle multiple multiplication factors (e.g., 2x, 3x, 4x, 6x) using the same basic circuit architecture. By making the circuit universal and reconfigurable, the patent avoids needing separate dedicated circuits for each multiplication factor, thereby reducing the overall die-area while maintaining high frequency multiplication capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The frequency multiplier uses dynamically controllable circuit elements that can be reconfigured based on the desired multiplication factor. This dynamic adaptability allows a single circuit to perform multiple functions, reducing the need for multiple fixed-function circuits and thereby minimizing die-area usage.

Inventive Principle:
Principle #15Dynamics

3Speed

If high-frequency LO signals are generated directly, then the signal frequency is improved, but the phase noise performance deteriorates

Engineering Contradiction:
Improvesignal frequencyVSAvoidphase noise performance
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The frequency multiplication process is segmented into multiple stages, each operating at a lower frequency than the final output. This segmentation allows each stage to operate with better phase noise characteristics, and the cumulative effect of multiple low-noise stages produces a high-frequency output with superior overall phase noise performance compared to direct single-stage generation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Intermediate frequency signals are used as mediators in the staged frequency multiplication process. Each intermediate signal serves as a clean, low-noise foundation for the next multiplication stage, preventing the accumulation and amplification of phase noise that would occur in direct high-frequency generation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12562745B2Apparatus, system, and method of a digitally-controlled frequency multiplier
Publication Date: 2026.02.24 INTEL CORP
  • US12562745B2 patent drawing
  • US12562745B2 patent drawing
  • US12562745B2 patent drawing

AI summary

For example, an apparatus may include a digitally-controlled frequency multiplier, which may be controllable according to a digital control input, to generate an output frequency signal having an output frequency, for example, by multiplying an input frequency of an input frequency signal. For example, the digitally-controlled frequency multiplier may include a phase generator configured to generate a plurality of phase-shifted signal groups corresponding to a respective plurality of first phase-shifts applied to the input frequency signal, a plurality of digital clock multipliers controllable according to the digital control input to generate a respective plurality of frequency-multiplied signals based on the plurality of phase-shifted signal groups, and a combiner to generate the output frequency signal based on a combination of the plurality of frequency-multiplied signals.