Configurable Digital Locked Loop for Phase Tracking and Power Balance
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Solution Overview
Problem
Conventional locked loops, such as delay lock loops and phase lock loops, lack the ability to easily adjust operating parameters like hysteresis and tracking speed, leading to performance limitations in various applications, as these parameters are not optimized for specific use cases.
Innovation Solution
Incorporating a phase detector with an adjustable hysteresis control and frequency dividers that can be enabled or disabled to adjust the tracking speed, allowing users to customize the loop's performance based on application needs, thereby optimizing power consumption and noise immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the hysteresis is reduced to achieve tighter phase tracking, then the phase accuracy is improved, but the power consumption increases due to more frequent delay line adjustments
Solution Approach 1:
The patent implements dynamic adjustment of the hysteresis parameter based on operating conditions. The control circuitry can modify the hysteresis width of the phase detector to optimize the trade-off between phase accuracy and power consumption. When high precision is needed, the hysteresis is reduced; when power savings are prioritized, the hysteresis is increased to reduce adjustment frequency.
Solution Approach 2:
The patent changes the hysteresis parameter dynamically to resolve the contradiction. By adjusting the hysteresis width as a controllable parameter, the system can adapt to different operating modes, achieving tight phase tracking when needed while conserving power during normal operation. This parameter adjustment is implemented through control signals that modify the phase detector's comparison thresholds.
2Measurement precision
If the tracking speed is increased to improve phase synchronization, then the phase accuracy is improved, but the power consumption increases due to more frequent phase comparisons
Solution Approach 1:
The patent implements dynamic adjustment of the tracking speed parameter. The control circuitry can modify how frequently the phase detector compares phases based on system needs. During initialization or when phase drift is detected, tracking speed is increased; during stable operation, tracking speed is reduced to conserve power while maintaining synchronization through the delay line's natural stability.
Solution Approach 2:
The patent uses periodic phase comparisons at variable intervals rather than continuous comparison. The frequency of phase comparison operations is adjusted dynamically - more frequent comparisons when synchronization is needed, less frequent comparisons when the system is stable. This periodic action with variable period resolves the contradiction between tracking speed and power consumption.
3Use of energy by moving object
If the hysteresis is increased to reduce power consumption, then the power consumption is reduced, but the noise immunity deteriorates
Solution Approach 1:
The patent dynamically adjusts the hysteresis parameter based on noise conditions and operational requirements. When noise is detected or during critical operations requiring stability, the hysteresis is reduced to improve noise immunity. During quiet operation or when power savings are critical, the hysteresis is increased. This dynamic adaptation resolves the contradiction between power consumption and noise immunity.
Solution Approach 2:
The patent employs feedback mechanisms where the system monitors phase stability and noise conditions, then adjusts the hysteresis parameter accordingly. If phase drift or noise is detected, the feedback loop reduces hysteresis to maintain stability. If operation is stable and power savings are needed, the feedback allows hysteresis to increase. This closed-loop control resolves the contradiction adaptively.
Data Source
AI summary
A locked loop may have an adjustable hysteresis and/or a tracking speed that can be programmed by a user of an electronic device containing the locked loop or controlled by an integrated circuit device containing the locked loop during operation of the device. The looked loop may include a phase detector having a variable hysteresis, which may be coupled to receive a reference clock signal and an output clock signal from a phase adjustment circuit through respective frequency dividers that can vary the rate at which the phase detector compares the phase of the output clock signal to the phase of the reference clock signal, thus varying the tracking speed of the loop. The hysteresis and tracking speed of the locked loop may be programmed using a variety of means, such as by a temperature sensor for the electronic device, a mode register, a memory device command decoder, etc.