Digital Noise Mask Filtering With Latch-Timed Glitch Suppression
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Solution Overview
Problem
Existing noise filtering circuits in digital systems struggle to effectively suppress multiple digital glitches and lack a memory device to control the duration of noise suppression, leading to erroneous system operation.
Innovation Solution
A circuit comprising a D-latch, timer, and logic circuit that generates a filter signal with defined states to mask digital noise, using an integrator and comparator to create a pre-defined duration pulse and an OR-gate to block spurious transitions, incorporating a current source and capacitor for efficient timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a switch, large capacitor, and weak pull-up current source are used to filter digital noise, then noise suppression is achieved, but it is difficult to control the duration of noise suppression and no memory device exists to suppress multiple glitches
Solution Approach 1:
An integrator circuit is introduced as an intermediary component between the digital signal and the output. The integrator accumulates the signal over time and produces a proportional output, enabling precise control of the noise suppression duration through its time constant rather than relying on complex RC networks or additional memory devices
Solution Approach 2:
The patent replaces traditional mechanical or complex electronic timing mechanisms (RC time constants, flip-flops, latches) with an integrator-based timing mechanism. This substitution simplifies the circuit by using the natural charging/discharging characteristics of the integrator capacitor to define the noise suppression window, eliminating the need for separate memory devices
2Duration of action of moving object
If RC time constant approach is used to generate timing pulse, then timing function is achieved, but area requirements increase
Solution Approach 1:
The integrator circuit serves multiple functions simultaneously: it acts as a timing element to define the noise suppression duration, functions as a low-pass filter to reject high-frequency noise, and provides signal conditioning for the comparator. This multi-functionality eliminates the need for separate RC timing networks and reduces overall circuit area
Solution Approach 2:
The patent changes the timing mechanism from RC time constants to an integrator-based time constant that can be precisely controlled by adjusting the integrator's feedback resistor or capacitor values. This parameter change enables more compact timing circuitry while maintaining accurate timing pulse generation
3Reliability
If traditional noise filtering circuit is used, then single glitch filtering is achieved, but multiple glitches cannot be suppressed
Solution Approach 1:
The integrator maintains a continuous accumulated signal that reflects the recent history of input transitions. This continuous integration naturally suppresses multiple glitches occurring within the integration time constant without requiring discrete memory devices or flip-flops to detect and block each glitch individually
Solution Approach 2:
The integrator acts as a memory-like intermediary that retains information about recent input states through its capacitor charge. This accumulated charge continues to influence the output during the noise suppression window, enabling automatic suppression of multiple glitches without additional memory circuitry
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses multiple glitches by using a memory device to control noise suppression duration, reducing area requirements and minimizing current consumption, while ensuring reliable system operation by generating a clean filtered digital signal.
Implementation Method 1
an integrator and comparator to create a pre-defined duration pulse
Implementation Method 2
a memory device to suppress multiple glitches
Implementation Method 3
an OR-gate to mask out the digital noise
Data Source
AI summary
A system and method for filtering spurious transitions from a digital signal is disclosed. The system includes a latch, a timer, and a logic circuit. Upon a transition of the digital signal, the latch holds the digital signal to block any additional transitions and the timer, which is connected to the output of the latch, begins a timing operation that creates a filter pulse. The output of the timer is then combined with the digital signal to filter the spurious transitions that may occur after the transition of the signal. The timer is implemented as an integrator that generates a ramp signal using a stable current source and a comparator that trips when the ramp signal passes a threshold. Use of the integrator and comparator saves space and reduces the system's operating current compared to the conventional approach.