Differential Digital Power Amplifier With Gate-Charge Reuse
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Solution Overview
Problem
Differential digital power amplifiers used in RFID antennas face efficiency losses due to the need for intermediate power supplies in small geometry semiconductor manufacturing processes, particularly when operating from a single lithium-ion battery supply voltage, leading to significant power consumption and reduced efficiency.
Innovation Solution
A differential digital power amplifier design that utilizes extended drain MOS transistors with a switch between high and low side driver voltages to create a voltage divider, allowing current reuse and reducing driver current consumption by 30%, thereby enhancing efficiency and power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If intermediate power supplies are used to drive gates of output transistors in small geometry processes, then the power amplifier can operate from a single supply voltage, but efficiency drops significantly due to power loss in internal pass devices
Solution Approach 1:
The patent recovers the charge stored in the gate-source capacitance of the high-side extended drain PMOS transistor and reuses it to drive the low-side extended drain NMOS transistor. This is achieved by connecting the gate of the low-side NMOS transistor to the source of the high-side PMOS transistor through a coupling capacitor, thereby recovering the charge that would otherwise be discarded and eliminating the need for separate intermediate power supplies
Solution Approach 2:
The patent merges the high-side and low-side driver circuits by using a single supply voltage and sharing the gate drive resources. The coupling capacitor enables the low-side driver to use the high-side driver's charge, effectively combining the two previously separate driver functions into a unified system that operates from a single supply
2Stability of the object's composition
If a DC-DC convertor is used to create constant output voltage from variable battery voltage, then the power amplifier can maintain stable operation, but efficiency is reduced due to losses in the DC-DC convertor
Solution Approach 1:
The patent makes the gate driver circuits self-sufficient by directly coupling them to the single supply voltage without requiring intermediate DC-DC conversion. The extended drain MOSFETs inherently tolerate the full supply voltage range, and the coupling capacitor provides automatic charge sharing, eliminating the need for external voltage regulation and allowing the system to adapt to battery voltage variations
3Reliability
If separate pre-driver stages with voltage regulators are used for extended drain MOS transistors, then gate-source voltages can be kept below maximum allowed levels, but total driver current consumption increases
Solution Approach 1:
The patent recovers the charge from the high-side PMOS gate-source capacitance and reuses it to drive the low-side NMOS transistor. The coupling capacitor captures the charge when the high-side transistor turns off and delivers it to the low-side transistor when needed, thereby recovering energy that would otherwise be wasted and reducing total current consumption by more than 30%
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
A differential digital power amplifier (1) to drive an RFID antenna (4) with a substantial sinusoidal output current with an RFID frequency which digital power amplifier (1) comprises: a digital control section (DCS) to output digital wave-forming bits (10) to a first group of driver blocks (6) and a second group of driver blocks (6) wherein a switch (27) between the source contact (21) of a first voltage follower transistor (16) and the source contact (26) of a second voltage follower transistor (22) to short circuit these source contacts (21, 26) to unload/load gate-source capacities (Cgs) of a drain extended PMOS transistors (5) with charge carriers used to load/unload gate-source capacities (Cgs) of the drain extended NMOS transistors (7) to reduce the driver current needed at gate contacts (12, 14) of the drain extended PMOS transistors (5) and drain extended NMOS transistors (7).