Digital-to-Phase Converter Windowing Without Secondary Delay Lines
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Solution Overview
Problem
Existing digital-to-phase converters (DPCs) suffer from windowing errors that result in inaccuracies in output signals due to the need for secondary delay lines, which increase the size and power dissipation of the device, making it impractical for multiple independent output terminals.
Innovation Solution
A windowing and selection circuit using sequential logic devices, such as D flip-flops and combinational logic, is introduced to select and generate output signals without requiring secondary delay lines, ensuring accurate timing and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If secondary delay lines are used to address windowing errors, then output signal accuracy is improved, but device size and power dissipation increase
Solution Approach 1:
The patent extracts and eliminates the secondary delay lines from the DPC architecture, removing the source of excessive power dissipation while maintaining output signal accuracy through an alternative windowing correction mechanism
Solution Approach 2:
The patent changes the operational parameters of the delay line by implementing variable delay element control that allows dynamic adjustment of delay values to correct windowing errors without requiring additional secondary delay lines, thereby reducing power consumption
2Measurement precision
If secondary delay lines are used to address windowing errors, then output signal accuracy is improved, but device complexity increases
Solution Approach 1:
The patent removes the complex secondary delay line structure from the DPC, simplifying the device architecture while maintaining the ability to correct windowing errors through control signal adjustments
Solution Approach 2:
The patent makes the existing delay elements multi-functional by enabling them to perform both their primary delay function and the secondary function of correcting windowing errors through dynamic control, eliminating the need for separate correction circuits
3Reliability
If secondary delay lines are used to address windowing errors, then windowing errors are corrected, but the solution becomes impractical for multiple independent output terminals
Solution Approach 1:
The patent segments the control of multiple output terminals by providing independent control signals for each terminal's delay elements, allowing each output to be independently optimized without requiring additional secondary delay lines for each terminal
Solution Approach 2:
The patent implements dynamic control of delay elements through programmable control signals that can be independently adjusted for each output terminal, enabling adaptive correction of windowing errors across multiple terminals without increasing hardware complexity
Data Source
AI summary
A DPC (300) includes: a frequency source (310) for generating a clock signal; a delay line (320) for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device (330) for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices (500, 510, 520) and a combining network. A method for use in a DPC includes: receiving (400) a control signal based on a desired output signal that identifies a first output tap on the delay line; based on the control signal, selecting (410) at least two output taps on the delay line for receiving at least two different phase-shifted clock signals; and generating (420) an output signal based on the control signal and the received phase-shifted clock signals that is substantially the desired output signal.