Frequency-Domain Digital PLL With Edge Randomization for Spur Control
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Solution Overview
Problem
Prior art phase-domain digital phase locked loops (DPLLs) face challenges such as infinite dynamic range requirements, meta-stability issues, substantial analog circuitry, and non-portability across semiconductor processes due to the need for time-to-digital conversion and analog design complexities.
Innovation Solution
A frequency-domain digital phase locked loop that samples the period of a reference frequency clock with a digitally controlled oscillator (DCO) clock, randomizes the arrival time of state transition edges to prevent quantization errors, and uses a loop filter to integrate frequency errors for control, eliminating the need for time-to-digital conversion and simplifying the design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If phase-domain DPLL is used to achieve fine phase resolution, then phase noise requirements are met, but substantial analog circuitry including TDC is required which increases area and current consumption
Solution Approach 1:
The patent replaces the analog time-to-digital converter (TDC) with a digital period measurement mechanism. Instead of using analog circuitry to measure phase differences with high precision, the invention samples the reference clock period using a digital counter driven by the DCO clock, converting the measurement into the digital domain where it can be processed without complex analog components.
Solution Approach 2:
The invention extracts and removes the TDC block from the PLL architecture entirely. By measuring the reference clock period in the digital domain through sampling and counting, the patent eliminates the need for the analog TDC component while maintaining the necessary measurement precision for phase noise requirements.
2Measurement precision
If TDC is used for time-to-digital conversion, then phase measurement is achieved, but analog impairments such as mismatch occur and portability across semiconductor processes is reduced
Solution Approach 1:
The patent substitutes the analog TDC with a fully digital period measurement approach. By using a digital counter to sample and measure the reference clock period, the invention eliminates analog impairments such as mismatch that plague TDC implementations, while maintaining measurement precision. This digital approach is inherently more portable across different semiconductor fabrication processes.
3Device complexity
If reference clock period is determined by sampling with DCO clock, then frequency domain operation is achieved, but quantization errors accumulate causing spurious emissions
Solution Approach 1:
The patent implements a feedback mechanism where the measured reference clock period is compared with the expected period derived from the DCO control word. The frequency error signal generated from this comparison is fed back through a loop filter to adjust the DCO control, creating a closed-loop system that corrects quantization errors and eliminates spurious emissions while maintaining the simplicity of frequency-domain operation.
4Reliability
If phase difference is converted to control voltage in analog PLL, then phase lock is achieved, but analog design knowledge is required and design is not portable
Solution Approach 1:
The patent replaces the analog phase-to-voltage conversion mechanism with a digital frequency-domain approach. Instead of using analog multipliers and low-pass filters to generate control voltage, the invention measures the reference clock period digitally, compares it with the expected period, and generates a digital control word for the DCO. This maintains reliable phase lock while making the design fully portable across semiconductor processes.
Data Source
AI summary
A digital phase locked loop (DPLL) operates in the frequency domain. The period (and hence frequency) of a reference frequency clock signal is determined by sampling with a (higher frequency) digitally controlled oscillator (DCO) clock. The period is compared to the period representation of a desired frequency, and the frequency error signal is integrated in a loop filter and applied as a control input to the DCO. To prevent spurious emissions resulting from the accumulation of quantization errors in the frequency determination and comparison operations, the arrival time of state transition edges of the reference frequency clock signal are randomized prior to sampling. The edge randomization control signal preferably has a triangular probability density function, and its spectrum has most significant energy outside the loop bandwidth of the DPLL; hence, the spurious emissions caused by the accumulation of quantization errors are filtered out by the loop filter.