Digital PLL Clock Holdover Using Sigma-Delta DCO Averaging
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Solution Overview
Problem
Existing digital clock systems face challenges in maintaining high stability and accuracy during holdover events while minimizing power consumption and reducing costs, as they require external components like filters and comparators, which increase complexity and cost.
Innovation Solution
A digitally-controlled oscillator (DCO) with a sigma-delta modulator, adder, and multi-modulus divider, along with a digital phase/frequency detector and buffer, allows for a persistent clock generation by averaging fractional frequency adjustments, eliminating the need for external filters and comparators, and using a stable source clock for continuous operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a DDS+DAC implementation is used to generate a digital clock, then the clock can be tuned digitally, but external filters and comparators are required which increase device complexity and cost
Solution Approach 1:
The patent combines the DDS, DAC, filter, and comparator functions into a single integrated DCO circuit block. The digitally-controlled oscillator integrates the digital-to-analog conversion and signal generation functions that were previously separate components, eliminating the need for external filters and comparators while maintaining digital tuning capability.
Solution Approach 2:
The DCO circuit block serves multiple functions simultaneously: it acts as a digital-to-analog converter, generates the clock signal, provides filtering through its internal architecture, and outputs both sine and square wave forms. This multi-functional integration reduces the overall system component count.
2Ease of operation
If external filter and comparator components are used in the clock system, then the clock can be generated with digital control, but the integration cost and power consumption increase
Solution Approach 1:
The patent merges previously discrete external components (filter and comparator) into the integrated DCO circuit block, allowing all functions to be manufactured together in a single semiconductor fabrication process. This integration eliminates the need for separate component assembly and reduces overall system cost.
3Productivity
If a DDS+DAC implementation with external filter is used, then the clock can be generated, but additional space is occupied and cost increases
Solution Approach 1:
The patent consolidates the DDS, DAC, filter, and comparator functions into a single DCO circuit block, significantly reducing the total circuit area required. By integrating these functions into one compact block rather than using separate discrete components, the overall space occupation in the clock system is minimized.
4Productivity
If the DPLL operates in holdover mode without reference clock, then the system can continue operating, but frequency accuracy and stability deteriorate
Solution Approach 1:
The patent pre-charges the holdover capacitor during normal operation when the reference clock is available. This preliminary charging stores energy and frequency information that can be used to maintain accurate clock operation during holdover events, improving frequency stability without requiring continuous reference input.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a highly stable and accurate clock system that operates during holdover events with reduced power consumption and lower integration costs, as it integrates key components within a common integrated circuit, maintaining clock stability and accuracy without external components.
Implementation Method 1
A digitally-controlled oscillator (DCO) with a sigma-delta modulator, adder, and multi-modulus divider, along with a digital phase/frequency detector and buffer, allows for a persistent clock generation by averaging fractional frequency adjustments
Data Source
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AI summary
A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitallycontrolled oscillator (DCa) including a sigma- delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock, a second input for a feedback signal, the DPFD generating an output representing a difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for accumulating the difference signal over time. The sigma-delta modulator (SDM) may have a control input coupled to the buffer. The adder may have inputs coupled to the (SDM) and a source of an integer control word.