Digital PLL Loop Filter Gain Control for Low Jitter Clocks
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Solution Overview
Problem
Existing digital phase locked loops (PLLs) suffer from high jitter and noise due to limited resolution in time-to-digital converters (TDCs), which affect the accuracy of phase difference detection and increase root mean square (RMS) jitter in oscillation signals.
Innovation Solution
A digital phase locked loop (PLL) with a digitally controlled oscillator (DCO), divider, time-to-digital converter (TDC), and digital loop filter, featuring adjustable gain and duty cycle control circuits to reduce jitter by filtering noise and adjusting frequency control signals based on error signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a digital phase locked loop uses a time-to-digital converter (TDC) with limited resolution, then the device complexity is reduced, but the measurement precision of phase difference detection deteriorates, leading to high jitter and noise
Solution Approach 1:
The patent introduces a digital loop filter as an intermediary component between the TDC and the DCO. This filter processes the error signal from the TDC, adjusting its gain and duty cycle to reduce noise and jitter before feeding back to the DCO. The digital loop filter acts as a mediator that compensates for the limited resolution of the TDC without requiring a higher-resolution converter, thus maintaining simple device architecture while improving measurement precision.
2Measurement precision
If the gain of the digital loop filter is increased to reduce noise, then the measurement precision improves, but the stability of the oscillation signal deteriorates due to increased jitter
Solution Approach 1:
The patent implements dynamic adjustment of the digital loop filter's gain and duty cycle based on the error signal characteristics. The gain/duty control circuit continuously adapts these parameters to optimize noise filtering while maintaining oscillation stability. This dynamic approach allows the system to achieve high measurement precision without sacrificing signal stability, as the filter parameters are optimized in real-time rather than fixed at high values that would cause jitter.
3Stability of the object's composition
If the duty cycle of the digital loop filter is adjusted to reduce jitter, then the stability of the oscillation signal improves, but the gain control becomes less effective, increasing noise
Solution Approach 1:
The patent designs the digital loop filter with a unified gain/duty control circuit that simultaneously manages both gain and duty cycle parameters. This multi-functional control mechanism allows the filter to coordinate adjustments of both parameters to achieve noise reduction and jitter suppression together, rather than treating them as separate conflicting objectives. The unified control ensures that duty cycle adjustments for stability do not compromise noise filtering effectiveness.
Data Source
AI summary
A digital phase-locked loop (PLL) includes: (i) a digitally controlled oscillator (DCO) configured to generate an oscillation signal having a frequency that is adjustable in response to a frequency control signal, (ii) a divider configured to generate a feedback signal in response to dividing a frequency of the oscillation signal, (iii) a time-to-digital converter (TDC) configured to detect a phase difference between a reference signal and the feedback signal, and generate an error signal having a value that is a function of the phase difference, and (iv) a digital loop filter configured to generate the frequency control signal in response to the error signal and the oscillation signal.