Digital Fractional-N PLL for Jitter Filtering and Crosstalk Immunity
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Solution Overview
Problem
Crosstalk between adjacent clock signal generators in communication systems, such as SONET and OTN, causes noise and crosstalk immunity issues, particularly with low bandwidth PLLs, which require large capacitors or costly VCXOs, and space constraints in integrated designs.
Innovation Solution
Implementing a PLL with a Digital Controlled Oscillator (DCO) and a fractional synthesizer, combining a low bandwidth digital filter with a wide bandwidth fractional-N PLL loop to suppress VCO noise and crosstalk, allowing for integration of cleanup PLLs on a single chip or board.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If low bandwidth PLLs are used to filter reference noise, then jitter filtering is improved, but crosstalk immunity deteriorates
Solution Approach 1:
The patent divides the PLL bandwidth control into two independent segments: a digital filter that sets the loop bandwidth to suppress VCO noise and crosstalk, and a separate reference noise filter that cleans reference clock jitter. This segmentation allows each filter to be optimized independently for its specific function without compromising the other performance aspect.
Solution Approach 2:
The patent changes the bandwidth parameter dynamically by using a digitally controllable filter that can adjust the loop bandwidth. This allows the system to optimize the bandwidth parameter for crosstalk suppression while maintaining effective reference noise filtering through the separate digital filter stage.
2Object-affected harmful factors
If wider bandwidth PLLs are used to reduce crosstalk, then crosstalk immunity is improved, but reference noise filtering deteriorates
Solution Approach 1:
The patent segments the noise filtering function into two independent filters: a digital filter that controls loop bandwidth for crosstalk suppression and a separate reference noise filter that targets reference clock jitter. This allows the bandwidth to be widened for crosstalk immunity while the reference noise filter maintains cleaning capability.
Solution Approach 2:
The patent introduces a digital filter as an intermediary component between the phase detector and the VCO. This digital filter acts as a mediator that shapes the loop bandwidth response to suppress crosstalk and VCO noise, while the reference noise filter separately handles reference clock cleaning, allowing both functions to coexist.
3Measurement precision
If analog filters with low bandwidth are used for jitter filtering, then jitter filtering is improved, but device complexity and area increase due to large capacitors
Solution Approach 1:
The patent replaces the mechanical/analog filter implementation with a digital filter implementation. Instead of using large physical capacitors and resistors that require significant board space and are difficult to integrate, the filter is implemented using digital logic circuits that can be easily integrated into standard CMOS or ASIC processes, dramatically reducing area and complexity.
Solution Approach 2:
The patent changes the implementation medium from analog to digital, allowing the same low-pass filtering function to be achieved with digital circuits. This parameter change enables the system to achieve equivalent or superior filtering performance with significantly reduced component size and integration complexity.
4Object-affected harmful factors
If multiple stand-alone cleanup PLLs are used to reduce crosstalk, then crosstalk immunity is improved, but cost and area increase
Solution Approach 1:
The patent merges multiple PLL functions into a single integrated cleanup PLL unit. By combining the reference noise filter and the VCO noise/crosstalk filter into one unified digital architecture, the system achieves the functionality of multiple separate PLLs while using significantly less area and reducing overall system complexity and cost.
Solution Approach 2:
The patent creates a universal cleanup PLL architecture that performs multiple functions: reference noise filtering, VCO noise suppression, and crosstalk rejection. This multi-functional digital filter design eliminates the need for separate dedicated circuits for each function, reducing overall system complexity and area while maintaining all required performance characteristics.
Data Source
AI summary
A phase difference between a reference clock signal and a feedback signal is digitally detected. A resultant phase detection signal is digitally filtered, and a PLL (Phase Locked Loop) output signal is synthesized in a fractional synthesizer under control of the digitally filtered phase detection signal. A feedback path, which could include an integer divider and/or a fractional N divider, provides the feedback signal based on the PLL output signal. The combination of a wide bandwidth fractional synthesizer and a low bandwidth digital PLL provides for a low bandwidth jitter filtering function with a wide bandwidth PLL to suppress VCO (Voltage Controlled Oscillator) noise and crosstalk.