Digital PLL Loop Gain Stepping for Fast Lock and Low Phase Noise
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Solution Overview
Problem
Existing digital phase-locked loops (PLLs) face challenges in transitioning from high bandwidth for rapid signal acquisition to low bandwidth for noise reduction, as abrupt changes in loop gain introduce significant transients that take time to settle, affecting overall performance.
Innovation Solution
A digital PLL with an adjustable loop gain mechanism that fine-grainedly adjusts bandwidth by using a sequence of loop gain adjustment circuits and a phase error detector, allowing for gradual changes from a high loop gain during acquisition to a low loop gain during tracking, with a loop filter circuit to manage these adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If loop gain is reduced to minimize phase noise and spurs, then signal tracking quality improves, but signal acquisition speed deteriorates
Solution Approach 1:
The patent implements dynamic adjustment of loop gain with multiple discrete levels, allowing the PLL to transition from a first loop gain value during signal acquisition to a second loop gain value for signal tracking. This dynamic adaptation resolves the contradiction by having high loop gain (fast acquisition) when needed and low loop gain (low noise) when needed, rather than being fixed at one value.
Solution Approach 2:
The patent changes the loop gain parameter between different operating modes. By switching the loop gain from a first value to a second value based on whether the PLL is in acquisition or tracking mode, the system optimizes performance for each mode while avoiding the harmful effects of using a single fixed parameter value.
2Productivity
If loop gain is abruptly switched from first value to second value, then bandwidth reduction is achieved, but significant transients are introduced into phase error
Solution Approach 1:
The patent segments the loop gain adjustment into multiple discrete levels rather than a single abrupt switch. The loop gain can be adjusted through intermediate values when transitioning from the first loop gain value to the second loop gain value, which reduces the magnitude of transients in the phase error while still achieving the desired bandwidth reduction.
3Speed
If type-I PLL is used for rapid acquisition, then signal acquisition speed improves, but phase noise and spurs increase
Solution Approach 1:
The patent makes the loop gain dynamic rather than fixed, allowing the PLL to operate with high loop gain (type-I characteristics) during acquisition for fast speed, then transition to low loop gain (type-II characteristics) during tracking for low noise. This dynamic reconfiguration allows the system to exhibit different effective characteristics in different operating modes.
Data Source
AI summary
System and method for improving a digital PLL's performance by making fine grained adjustments to the loop gain. A preferred embodiment comprises a plurality of loop gain adjustors (such as loop gain adjustors 605, 606, 607, and 608) that can incrementally adjust the loop gain. The incrementally adjusted loop gains are sequentially brought on-line so that the loop gain of the digital PLL is slowly decreased. By slowly decreasing the loop gain, the digital PLL is less perturbed by smaller noise transients that would take time to settle. Hence, the digital PLL can quickly acquire a signal and then decrease its loop gain and hence its bandwidth when it only needs to track a signal. The reduced bandwidth also reduces the overall noise in the digital PLL that is due to the reference noise contribution.