Digital PLL Phase Alignment for Faster Clock Locking
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Solution Overview
Problem
Designing a satisfactory phase-locked loop (PLL) for wireless communications circuitry in electronic devices is challenging due to uncertainties in the initial phase and frequency divider activation, leading to longer convergence times and synchronization issues across different clock domains.
Innovation Solution
Implementing a digital phase alignment circuit within the PLL that includes a time-to-digital converter, frequency divider, and sigma delta modulator, with components like multipliers, combiners, and multiplexers to adjust the feedback clock signal, ensuring it is within a well-defined range for faster phase locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional phase-locked loop is designed for wireless communications circuitry, then the basic PLL functionality is achieved, but the locking time is extended and synchronization issues occur across different clock domains
Solution Approach 1:
The patent applies preliminary action by performing phase alignment of the feedback clock signal before the PLL loop is closed. The phase alignment circuit adjusts the phase of the feedback clock signal in advance, ensuring that when the loop closes, the phase error is already minimized. This pre-adjustment mechanism significantly reduces the locking time while maintaining synchronization accuracy across different clock domains.
2Use of energy by moving object
If a conventional phase-locked loop operates with standard reference clock frequencies, then basic operation is maintained, but power savings are limited and locking time cannot be optimized
Solution Approach 1:
The patent applies parameter changes by enabling the PLL to operate with slower reference clock frequencies while maintaining effective locking performance. The phase alignment circuit compensates for the slower clock speed by pre-adjusting the feedback clock phase, allowing the system to reduce power consumption through lower frequency operation without sacrificing locking time performance. This parameter adjustment optimizes both power efficiency and timing characteristics.
Data Source
AI summary
Wireless circuitry may include phase-locked loop (PLL) circuitry. The PLL circuitry can include a time-to-digital converter (TDC) having a first input configured to receive a reference clock signal, a second input configured to receive a feedback clock signal, and an output at which a measured phase error is produced, a frequency divider configured to output the feedback clock signal, and a phase alignment circuit configured to output a corrected phase error that is used in adjusting the frequency divider. The phase alignment circuit can include a scaling component configured to scale the measured phase error by a phase alignment coefficient to produce a corresponding scaled phase error and a multiplexing component configured to selectively output a corrected phase error that is used in controlling a sigma delta modulator coupled to the divider.