Digital PLL Clock Generation With Oversampled Phase Detection
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Solution Overview
Problem
Digital phase-locked loops (PLLs) face challenges in accurately regulating clock frequencies due to regions where the phase detector fails to provide information about phase deviations between reference and local clock signals, leading to incorrect sampling and disturbances in digital data processing.
Innovation Solution
A system clock signal independent of the reference and local clock signals, with a frequency at least five times higher, is used to determine the temporal spacing between sampling pulses, allowing for 'oversampling' and precise regulation by ensuring the phase detector acquires information on phase shifts without interruption, and a jitter generator configures the sequence of undelayed and delayed clock signals for targeted frequency control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a digital phase-locked loop is used to regulate clock frequency, then the system complexity is reduced compared to analog PLLs, but the phase detector fails to provide information about phase deviations in certain regions, leading to incorrect sampling
Solution Approach 1:
The patent applies periodic action by using a multiplexer to alternately switch between different delay circuit configurations, feeding the clock signal with different temporal spacings to the phase detector. This periodic switching ensures that the phase detector continuously receives valid phase deviation information without interruption, resolving the reliability issue while maintaining digital system simplicity
Solution Approach 2:
The patent introduces a multiplexer as an intermediary component that selectively switches between direct and delayed clock signal paths. This intermediary ensures continuous valid phase information is provided to the phase detector, solving the information gap problem without adding significant complexity to the digital PLL system
2Ease of operation
If the phase detector samples phase deviation at fixed intervals determined by the common clock signal, then the system operation is simplified, but incorrect sampling occurs when phase shifts happen between sampling pulses
Solution Approach 1:
The patent applies dynamics by making the temporal spacing of clock signals fed to the phase detector variable through the multiplexer and delay circuit. By dynamically adjusting the spacing between clock signal edges presented to the phase detector, the system ensures that phase deviations are always captured, improving measurement precision while maintaining operational simplicity through automated switching
Solution Approach 2:
The patent implements feedback by using the phase detector's output to continuously regulate the oscillator, which in turn generates the local clock signal. The multiplexer ensures this feedback loop operates without interruption by guaranteeing continuous valid phase deviation information, thereby improving measurement precision while keeping the feedback mechanism simple
Data Source
AI summary
A method and apparatus generates a clock frequency dependent on a reference clock signal and has a phase locked loop configuration. A multiplexer is connected into the transmission path of the respective incoming input signal, to which the corresponding input signal is fed directly, on the one hand, and in delayed fashion, on the other hand. The common clock signal used is a system clock signal, independent of the reference clock signal and the local clock signal and whose frequency is higher by a factor of at least “5” than the frequency of the reference clock signal and of the local clock signal, respectively. The temporal spacing between the edges of the undelayed clock signal, and of the delayed clock signal, is set such that it is greater than the temporal spacing of the sampling pulses of the phase detector that are predetermined by the system clock signal.