All-Digital PLL Timing Correction for TDC Quantization Error
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Solution Overview
Problem
Radio frequency synthesizers using digital phase lock loops face quantization errors due to delays and skews in time to digital converters, leading to incorrect time differences and control signals for digitally controlled oscillators.
Innovation Solution
The implementation of a digital phase lock loop circuit comprising a digitally controlled oscillator, digital processor, phase acquisition circuit, counter, and time to digital converter, with a dithering circuit that adds random noise to the reference clock or feedback signal to distribute energy outside the bandwidth of the phase lock loop, reducing quantization errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If a time to digital converter is used to determine time difference in a digital phase lock loop, then the system can operate in all-digital domain, but quantization errors occur due to delays and skews causing incorrect time difference measurement
Solution Approach 1:
A dithering circuit is introduced as an intermediary component that adds a dithering signal to the reference clock or feedback signal. This mediator converts the harmful quantization errors into reduced noise by randomizing the quantization process, thereby improving measurement precision while maintaining all-digital operation.
Solution Approach 2:
The system changes the temporal parameters of the input signals by adding a time-varying dithering signal. This parameter change transforms the static quantization error into a dynamic process where the error is randomized and subsequently filtered, improving the accuracy of time difference measurement.
2Measurement precision
If dithering is added to the reference clock or feedback signal, then quantization errors are reduced, but the device complexity increases due to additional dithering circuit
Solution Approach 1:
The dithering circuit serves as a compact intermediary that can be integrated into the existing phase lock loop architecture. By positioning it at the input stage, it provides quantization error reduction without requiring complex modifications throughout the entire system, thus limiting the increase in device complexity.
3Measurement precision
If dithering signal is added to randomize quantization noise, then measurement accuracy improves, but energy is consumed by the dithering circuit
Solution Approach 1:
The dithering circuit adds only a small amplitude signal just sufficient to randomize the quantization error, rather than using excessive energy. This partial action approach achieves the necessary noise randomization while minimizing energy consumption, as the dithering signal level is kept low but effective.
Data Source
AI summary
An all-digital phase locked loop includes a time to digital converter that determines a fractional portion of a phase count. The time to digital converter has a quantization error that may be caused by phase noise, delay errors or skew errors. Several methods and devices may reduce the quantization error. A noise source may add dithering to the reference clock at an input of the time to digital converter. A digital processor may use two successive rising edges of the oscillator signal to count time delays of the time to digital convertor to the reference clock. The digital processor uses these counts to determine a ratio of the time delays and the time period of the oscillator signal for controlling a digitally controlled oscillator. A radio frequency counter circuit detects whether the oscillator signal leads or lags the reference clock because of skew and generates a phase signal to correct the skew.