Digital PLL Time Synchronization Against Ultra-Low Frequency Wander

The patent replaces voltage-controlled oscillators (VCOs) with digital controlled oscillators (DCOs) in the PLL circuits. This substitution transitions from an analog-based frequency control mechanism to a digital one, enabling the system to function as a high-pass filter that effectively removes ultra-low frequency wander components while maintaining frequency synchronization capability. The DCO-based implementation allows for precise digital control of the oscillation frequency, eliminating the analog vulnerabilities that previously allowed ultra-low frequency wander to pass through.

The patent replaces analog voltage control circuits with digital control circuits in the PLL architecture. The DCO is controlled by digital signals generated from the phase detector and loop filter, eliminating the need for analog voltage-controlled elements. This digitalization simplifies the circuit design, reduces component count, lowers manufacturing costs, and decreases power consumption while preserving the essential frequency control function. The digital implementation also improves reliability by reducing susceptibility to environmental factors like temperature and humidity that affect analog circuits.