Digital Power Gating with Programmable Bulk Voltage Control
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Solution Overview
Problem
Conventional power gating techniques are inefficient as they often result in data loss and require significant latency to save and restore state information, leading to high costs in terms of performance, especially in large-scale circuits like microprocessors, due to the inability to retain state during power gating and the need for full power cycling.
Innovation Solution
A digital power gating system with state retention that reduces the supply voltage to a target level to minimize leakage current while maintaining state information, using a programmable control system to adjust voltage levels during power gating and resume operations, allowing for efficient power saving and seamless resumption of operations without data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional power gating techniques are used to reduce power consumption, then power consumption is reduced, but sub-threshold leakage current causes significant power wastage
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the bulk voltage of CMOS devices during power gating operations. The bulk voltage is modulated to counteract sub-threshold leakage current, transforming a static parameter into a dynamic control variable that optimizes power consumption while minimizing leakage losses in advanced technology nodes
Solution Approach 2:
The patent implements feedback mechanisms that monitor power consumption and leakage current levels, then adjust bulk voltage accordingly. This closed-loop control system continuously optimizes the balance between power savings and leakage reduction, ensuring efficient power gating operation in response to changing circuit conditions
2Reliability
If state retention mechanisms are implemented during power gating, then state retention is maintained, but latency is incurred during power-down and power-up cycles
Solution Approach 1:
The patent applies preliminary action by preparing retention circuits and control mechanisms before actual power gating occurs. Bulk voltage is pre-adjusted and retention structures are pre-configured to minimize the time required during power-down and power-up transitions, reducing latency while maintaining state integrity
Solution Approach 2:
The patent implements dynamic control of bulk voltage and power gating timing based on circuit state and operational requirements. This dynamic approach allows the system to optimize between state retention reliability and transition speed, adapting power gating parameters in real-time to minimize latency while preserving circuit state
Data Source
AI summary
An integrated circuit including a global supply bus, a gated supply bus, a functional circuit coupled to the gated supply bus, a programmable device that stores a programmed control parameter, and a digital power gating system. The digital power gating system includes gating devices and a power gating control system. Each gating device is coupled between the global and gated supply buses and each has a control terminal. The power gating control system controls a digital control value to control activation of the gating devices. The power gating control system is configured to perform a power gating operation by adjusting the digital control value to control a voltage of the gated supply bus relative to the voltage of the global supply bus. The power gating operation may be adjusted using the programmed control parameter. The programmable device may be a fuse array or a memory programmed with programmed control parameter.