Digital PWM Demodulator Using Bidirectional Delay Cells
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Solution Overview
Problem
Existing digital demodulation techniques for pulse-width modulated (PWM) signals are complex and not easily scalable, particularly due to the need for high-frequency clocks or complex analog circuitry.
Innovation Solution
A receiver with multiple delay cells configured in series to propagate PWM signals in both forward and reverse directions, using flip-flops to determine the data value based on feedback signals generated during these configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog techniques are used to charge and discharge capacitors during PWM signal demodulation, then demodulation can be achieved, but the circuit design becomes complex and layout effort increases
Solution Approach 1:
The patent replaces analog capacitor charging/discharging mechanisms with a digital delay line system. Instead of using analog components (capacitors, comparators) to demodulate PWM signals, the invention uses digital delay elements arranged in a series chain that propagate signals through fixed time delays, converting the analog demodulation problem into a digital timing problem that is easier to implement and scale.
Solution Approach 2:
The patent creates multiple delayed copies of the PWM signal through the series chain of delay elements. Each delay element produces a time-delayed version of the input signal, and these copied delayed signals are then combined through logical operations to extract the modulated data, avoiding the need for complex analog circuitry.
2Measurement precision
If a counter operated with a very high speed clock is used for PWM demodulation, then counting accuracy improves, but the system requires GigaHertz frequency clocks which increases complexity
Solution Approach 1:
The patent uses periodic clock signals at standard digital frequencies (not GigaHertz) to control the operation of delay elements and flip-flops. The demodulation is achieved through synchronized periodic sampling and delayed signal comparison, eliminating the need for extremely high-frequency clocks while maintaining measurement precision through proper timing relationships.
Solution Approach 2:
The patent introduces delay elements as intermediary components between the PWM input and the data output. These delay elements act as mediators that create precise time relationships between signal edges without requiring high-speed counting, allowing accurate demodulation at lower clock frequencies through controlled signal propagation delays.
3Reliability
If analog capacitor charging/discharging methods are used, then PWM demodulation is achieved, but scalability with respect to PWM signal frequency is limited
Solution Approach 1:
The patent implements a dynamic delay line system where the operation of delay elements can be controlled adaptively. The system can adjust its operation mode (forward propagation, reverse propagation, reset phases) based on the PWM signal characteristics, enabling it to scale to different frequencies without changing the fundamental circuit architecture, unlike fixed analog RC time constants.
Data Source
AI summary
A digital PWM demodulator includes a first set of delay cells to receive a PWM signal and to propagate the PWM signal in a forward direction for a first interval. Delayed signals obtained at the end of the first interval are propagated in the reverse direction through the delay cells for a second interval. A logic zero feeds into the last cell at the start of the second interval. The output of a last cell in the delay cells at the end of the second interval is indicative of a data value modulated on the PWM signal. The digital PWM demodulator includes a second set of delay cells designed to operate identical to the first set of delay cells. The first set of delay cells and the second set of delay cells in conjunction with additional digital circuitry demodulate alternate periods of the PWM signal.