Digitline Void-Space Formation for Memory Array Isolation

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Solution Overview

Problem

Current memory array technologies face challenges in efficiently forming vertically-stacked memory cells with direct electrical coupling to digitlines, which affects the reliability and performance of memory arrays, particularly in NAND architecture.

Innovation Solution

The method involves forming digitlines directly electrically coupled to memory cells, using a 'gate-last' or 'replacement-gate' processing approach, with channel openings etched through insulative and conductive tiers to ensure direct coupling, and selectively growing insulative material to create void-spaces between digitlines, enhancing electrical isolation and reducing parasitic capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If vertically-stacked memory cells are formed with conventional processing approaches, then memory array structure is achieved, but electrical coupling reliability to digitlines deteriorates

Engineering Contradiction:

Improveelectrical coupling reliabilityVSAvoidprocessing approach complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming channel openings through insulative and conductive tiers before forming the digitlines. This ensures that the digitlines can be directly coupled to the memory cells without requiring complex post-processing steps, thereby improving electrical coupling reliability while managing processing complexity

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent uses an intermediary approach by introducing conductive tiers and insulative tiers as intermediate structures between the memory cells and digitlines. These intermediary layers facilitate direct electrical coupling while providing necessary electrical isolation and structural support

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If digitlines are formed with direct electrical coupling to memory cells, then electrical coupling efficiency is improved, but parasitic capacitance increases

Engineering Contradiction:

Improveelectrical coupling efficiencyVSAvoidparasitic capacitance

Core Design Contradiction:

ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by selectively growing insulative material in specific regions between adjacent digitlines. This creates localized void-spaces only where needed to reduce parasitic capacitance, while maintaining direct electrical coupling efficiency at the memory cell interfaces. The insulative material is deposited only on exposed surfaces of the digitlines, providing targeted capacitance reduction without compromising overall coupling efficiency

Inventive Principle:

Principle #3Local quality

3Reliability

If insulative material is grown to create void-spaces between digitlines, then electrical isolation is enhanced, but manufacturing complexity increases

Engineering Contradiction:

Improveelectrical isolationVSAvoidmanufacturing process simplicity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies self-service by using selective material growth from the exposed surfaces of the digitlines themselves. The insulative material grows automatically from the digitline surfaces into the void-spaces, using the digitlines as their own templates. This self-service approach enhances electrical isolation while minimizing manufacturing complexity, as the process requires no additional masking or patterning steps

Inventive Principle:

Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables reliable and efficient formation of memory arrays with improved electrical coupling and reduced capacitance, enhancing the performance and retention of memory cells in vertically-stacked configurations.

Implementation Method 1

Insulative material is selectively grown from the exposed conductive digitline material relative to the masking material across the upwardly-open void-spaces to form covered void-spaces

Methodology Applied

Scientific EffectSelective deposition: Deposition (physical)

Data Source

PatentUS11640837B2Memory arrays and methods used in forming a memory array

Publication Date: 2023.05.02 MICRON TECHNOLOGY INC

AI summary

A method used in forming a memory array comprises forming digitlines above and electrically couple to memory cells there-below. The digitlines are laterally-spaced relative one another in a vertical cross-section. An upwardly-open void-space is laterally-between immediately-adjacent of the digitlines in the vertical cross-section. Conductive material of the digitlines is covered with masking material that is in and less-than-fills the upwardly-open void-spaces. The masking material is removed from being directly above tops of the digitlines to expose the conductive digitline material and to leave the masking material over sidewalls of the conductive digitline material in the upwardly-open void-spaces. Insulative material is selectively grown from the exposed conductive digitline material relative to the masking material across the upwardly-open void-spaces to form covered void-spaces there-from between the immediately-adjacent digitlines in the vertical cross-section. Structures independent of method are disclosed.