DIMM Clock Driver PLL Switching for Low-Jitter Power Management
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Solution Overview
Problem
Current clock drivers for dual in-line memory modules (DIMMs) face challenges in managing clock signals effectively, particularly with increasing frequencies leading to jittering issues, and require either more power for flexibility or less power with reduced flexibility in power management depending on the phase locking loop (PLL) mode.
Innovation Solution
A clock driver with one-PLL circuitry and a two-input clock signal mechanism, utilizing an input multiplexer, phase locking loop, output multiplexers, and a control module to selectively output clock signals and manage power based on input clock signal toggling, allowing for flexible power management similar to the two-PLL mode while maintaining equivalent power consumption to the single-PLL mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two-PLL mode is used to drive subchannels, then flexibility on per subchannel power management is improved, but normal operation power consumption increases
Solution Approach 1:
The patent implements dynamic selection between single-PLL and dual-PLL modes based on operational requirements. The system can switch between using one PLL for both subchannels or two separate PLLs for each subchannel, allowing adaptive power management that balances flexibility and energy consumption based on current workload and performance needs
Solution Approach 2:
A single PLL circuit is designed to serve dual purposes by generating clock signals for both subchannels when needed, while also being capable of dedicated operation for individual subchannels when flexibility is required. This multi-functional design eliminates the need for always having two separate PLL circuits
2Use of energy by moving object
If single-PLL mode is used to drive subchannels, then normal operation power is reduced, but flexibility on per subchannel power management is reduced
Solution Approach 1:
The system dynamically switches between single-PLL and dual-PLL operational modes based on power management requirements. When power savings are prioritized, a single PLL serves both subchannels; when per-subchannel control is needed, the system transitions to dual-PLL mode, providing adaptive response to changing operational conditions
3Productivity
If clock signal frequency is increased to improve performance, then productivity is improved, but jittering problem becomes more severe
Solution Approach 1:
The patent introduces an on-board clock driver as an intermediary component between the host controller and memory chips. This clock driver receives clock signals from the host controller and generates refined clock signals for the memory chips, acting as a buffer that reduces jittering effects while allowing high-frequency operation
Data Source
AI summary
A clock driver comprises: an input multiplexer for receiving a plurality pairs of input clock signals and an input selection signal, and for selectively outputting one pair of the plurality pairs of input clock signals according to the input selection signal; a phase locking loop (PLL) coupled to the input multiplexer to receive one pair of the plurality pairs of input clock signals, and for generating a PLL clock signal according to the received pair of input clock signals; at least two sets of output multiplexers coupled to the PLL to receive the PLL clock signal and an output selection signal, wherein each set of output multiplexers are configured to selectively output the PLL clock signal as a set of output clock signals according to the output selection signal to drive at least one group of memory chips; and a control module configured to detect toggling of the plurality pairs of input clock signals and generate the input selection signal and the output selection signal based on a detection result of the toggling of the plurality pairs of input clock signals.