Diode-Buffer Cell Layout for Antenna Effect Suppression
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Solution Overview
Problem
The accumulation of charge in long wirings during the etching process of a metal wiring layer in semiconductor devices can lead to insulation damage and leak currents due to the antenna effect, which is not effectively addressed by existing technologies.
Innovation Solution
Integration of a diode buffer cell that combines a diode and a buffer into a single cell, utilizing p-type and n-type impurity regions to prevent charge accumulation and ground the substrate, thereby eliminating the antenna effect and simplifying routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a diode cell is placed to block charge flow and prevent antenna effect, then product reliability is improved, but device complexity and routing complexity increase
Solution Approach 1:
The patent combines the diode cell and buffer cell into a single integrated structure. The diode cell includes first and second impurity regions with a first gate wiring between them, while the buffer cell includes third and fourth impurity regions with a second gate wiring. Both cells share the same substrate and are interconnected through wiring, merging their functions into one compact unit that prevents antenna effect while maintaining signal buffering capability.
Solution Approach 2:
The integrated cell structure serves multiple functions simultaneously: the diode portion blocks charge flow to prevent antenna effect, the buffer portion maintains signal integrity, and the shared wiring structure reduces overall device complexity. This multi-functional design allows a single cell to replace what would traditionally require separate diode and buffer cells.
2Reliability
If separate diode cell and buffer cell are used to prevent charge accumulation, then charge blocking function is achieved, but routing becomes more complex
Solution Approach 1:
The patent merges the diode cell and buffer cell into a single integrated structure with shared substrate and interconnected wiring. The first gate wiring and second gate wiring are both connected to the substrate through shared connection points, simplifying the routing architecture compared to separate cells that would require independent wiring paths.
3Reliability
If traditional separate diode and buffer cells are used, then charge accumulation is prevented, but input capacitance is higher
Solution Approach 1:
The integrated cell structure combines the diode and buffer functions in a single unit with shared substrate and wiring. This merging reduces the total input capacitance compared to separate cells because the gate wirings and impurity regions are optimally positioned and interconnected, minimizing parasitic capacitance while maintaining charge blocking functionality.
Data Source
AI summary
A semiconductor device comprises a first wiring that receives an input signal and extends in a first direction, a first gate wiring that extends in a second direction that intersects the first direction, a first impurity region disposed on one side of the first gate wiring and is connected to the first wiring, a second impurity region disposed on an other side of the first gate wiring and is connected to the first wiring, a second gate wiring that extends in the second direction and is spaced apart from the first gate wiring in the first direction and is connected to the first wiring, and a first inverter that includes the second gate wiring and is connected to the first wiring through which the inverter receives the input signal.