Diode Protection for Memory Cells Against In-Process Charging

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Solution Overview

Problem

In-process charging effects during the manufacturing of metal-oxide-semiconductor (MOS) integrated circuits, particularly in plasma enhanced processing, can cause yield and reliability issues, and existing protection methods like PN diode protection and poly fuse protection have limitations such as voltage restrictions and potential device disturbance.

Innovation Solution

A method involving connecting a memory cell line to a forward diode that turns on a conductive path to discharge in-process charges to ground during fabrication and reversely biases the diode during operation, using a control circuit with transistors to manage the diode's voltage states, ensuring protection without disrupting normal memory operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If PN diode protection or poly fuse protection is adopted, then in-process charging effects are protected, but voltage restrictions and device disturbance occur

Engineering Contradiction:
Improveprotection from in-process charging effectsVSAvoidvoltage restrictions and device disturbance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

An n-channel MOSFET is introduced as an intermediary switching device between the memory cell line and ground. The MOSFET acts as a controlled conductor that can be activated during fabrication to discharge in-process charges, then deactivated during operation to prevent voltage restrictions and device disturbance. This intermediary provides precise temporal control over the discharge path, eliminating the harmful effects of continuous diode-based protection schemes.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If antenna rules are enforced to check allowable ratio of metal gate to gate area, then in-process charging is controlled, but routing complexity and design flexibility are reduced

Engineering Contradiction:
Improvecontrol of in-process chargingVSAvoidrouting complexity and design flexibility
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The protection function is extracted from the signal routing paths and implemented as a separate, dedicated discharge mechanism using MOSFET switches. This extraction allows the memory cell lines to be routed freely without needing to satisfy antenna ratio constraints, as the discharge path is provided independently through the MOSFET switches connected to ground, rather than being embedded in the metal routing layers.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If reverse diode is added away from transistor source/drain, then antenna rule violation is fixed, but device area and circuit complexity increase

Engineering Contradiction:
Improveantenna rule complianceVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The discharge switch function is merged with the existing transistor structure by using an n-channel MOSFET whose source is connected to ground and whose drain connects to the memory cell line. This merging approach reuses the ground connection already present in the circuit and integrates the protection function into the existing device layout, minimizing additional area compared to adding separate reverse diodes away from the transistor structure.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Effectively prevents in-process charging damage by discharging accumulated charges to ground during manufacturing and maintaining the diode under reverse bias during operation, enhancing the reliability and yield of memory cells while avoiding the limitations of existing protection methods.

Implementation Method 1

in-process charges accumulated on the memory cells are discharged to a ground via a conductive path formed by a first voltage caused by the in-process charges forward biasing the diode

Methodology Applied
Scientific EffectForward biasing: Diode

Implementation Method 2

turning off the conductive path by reverse biasing the diode with a second voltage applied on the control circuit

Methodology Applied
Scientific EffectReverse biasing: Diode

Data Source

PatentUS20190206498A1Protecting memory cells from in-process charging effects
Publication Date: 2019.07.04 MACRONIX INTERNATIONAL CO LTD
  • US20190206498A1 patent drawing
  • US20190206498A1 patent drawing
  • US20190206498A1 patent drawing

AI summary

Systems, methods, circuits, and apparatus including computer-readable mediums for protecting memory cells from in-process charging effects for a memory system, e.g., NAND flash memory. The methods include: forming a first connection to connect a first node of a diode to a memory cell line coupled with one or more memory cells to be fabricated and a second connection to connect a second node of the diode to a control circuit, such that, during fabricating the memory, in-process charges accumulated on the memory cells are discharged to a ground via a conductive path formed by a first voltage caused by the in-process charges forward biasing the diode and then enabling the control circuit to conduct a current to the ground, and after fabricating the memory and during operating the memory, turning off the conductive path by reverse biasing the diode with a second voltage applied on the control circuit.