Direct Cache-to-Cache Data Transfer via Handshaking Signals
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Solution Overview
Problem
Existing techniques for data transfer between caches in heterogeneous multicore systems require substantial performance and power resources, leading to undesirable latency and inefficiency, especially in devices with limited power and performance potential like wireless devices.
Innovation Solution
The use of handshaking signals between processors to enable direct data transfer between caches without relying on system memory or cache coherency mechanisms, allowing a cache to function as tightly coupled memory for another processor, thereby reducing the need for external memory access and minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transferred through system memory using cache coherency mechanisms, then data integrity between processors is ensured, but latency increases and power consumption rises
Solution Approach 1:
The patent extracts the data transfer operation from the general cache coherency mechanism and creates a dedicated direct cache-to-cache transfer path. This separation allows data to be transferred directly between caches without involving system memory, thereby reducing latency while maintaining data integrity through dedicated transfer protocols and handshaking mechanisms.
Solution Approach 2:
The patent introduces a message passing intermediary system that facilitates direct communication between processor caches. Messages are exchanged between processors to coordinate data transfers, enabling synchronized data movement without requiring system memory involvement, thus reducing both latency and power consumption while ensuring data consistency.
2Adaptability or versatility
If data is flushed from local cache to system memory for transfer, then data can be shared between processors, but performance resources are substantially consumed
Solution Approach 1:
The patent merges the data sharing functionality directly into the cache subsystem by enabling direct cache-to-cache transfers. This integration eliminates the need to flush data to system memory and back, allowing processors to share data efficiently through direct cache connections, thereby maintaining data sharing capability while dramatically improving performance efficiency.
Solution Approach 2:
The patent segments the memory hierarchy by creating direct communication pathways between cache subsystems of different processors. This segmentation allows data to be transferred between caches without involving the general-purpose system memory, reducing the performance overhead associated with memory access while preserving data sharing capabilities across processors.
3Reliability
If cache coherency mechanisms are used to track processor access rights, then data integrity is maintained, but device complexity increases
Solution Approach 1:
The patent extracts the data integrity assurance function from the complex general cache coherency mechanism and implements it through simplified direct transfer protocols. By separating this function and implementing it through dedicated message passing and handshaking between caches, the system maintains data integrity while reducing overall device complexity.
Solution Approach 2:
The patent enables caches to self-coordinate data transfers through message passing between processors. Each processor and its cache autonomously manage data transfer operations and integrity verification through direct communication, eliminating the need for complex centralized cache coherency management and reducing system complexity while maintaining data integrity.
Data Source
AI summary
A method of transferring data between two caches comprises sending a first message from a first processor to a second processor indicating that data is available for transfer from a first cache associated with the first processor, requesting, from the second processor, a data transfer of the data from the first cache to a second cache associated with the second processor, transferring the data from the first cache to the second cache in response to the request, and sending a second message from the second processor to the first processor indicating that the data transfer is complete.