Direct Wirebonding on Exposed Vias for Compact Die Stacks
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Solution Overview
Problem
Existing stacked semiconductor devices face issues with bond fingers and bond pads corroding and occupying valuable space, leading to potential damage and increased size due to the need for additional routing structures.
Innovation Solution
The solution involves forming a package substrate with conductive vias and interconnects using a laser-drilling process, allowing direct wirebonding to the upper surfaces of these features without bond fingers, and incorporating insulation layers to protect routing lines and reduce exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bond fingers and bond pads are used to establish electrical communication routes, then electrical connection is achieved, but corrosion risk increases and device size increases
Solution Approach 1:
The patent removes bond fingers and bond pads from the electrical communication route, extracting the problematic intermediate structures that are prone to corrosion. Instead, wirebonds are directly bonded to conductive vias and interconnects, eliminating the corrosion-prone bond fingers and bond pads while maintaining electrical connectivity.
Solution Approach 2:
The patent merges the functions of bond fingers and bond pads directly into the conductive via structure. The wirebond is directly bonded to the conductive via, combining multiple functions (electrical connection, mechanical support, and routing) into a single integrated structure, thereby reducing the number of components and potential corrosion sites.
2Reliability
If additional routing structures are added to establish electrical communication, then electrical connection is achieved, but device size increases
Solution Approach 1:
The patent extracts and eliminates the need for additional routing structures such as bond fingers and bond pads by directly bonding wirebonds to conductive vias. This reduction in intermediate structures decreases the device footprint while maintaining reliable electrical connections through the streamlined path.
Solution Approach 2:
The patent utilizes the vertical dimension by bonding wirebonds directly to the upper surfaces of conductive vias and interconnects that extend through the package substrate. This vertical integration allows electrical connections to be established without occupying additional horizontal space, thereby reducing device footprint.
3Area of stationary object
If wirebonds are directly bonded to conductive vias and interconnects, then space is optimized and signal travel length is reduced, but direct bonding capability is required
Solution Approach 1:
The patent performs preliminary actions by forming conductive vias and interconnects with exposed upper surfaces that are specifically prepared for direct wirebond attachment. The conductive structures are pre-configured with appropriate surface properties and geometries during the substrate fabrication process, enabling subsequent direct wirebonding without requiring additional intermediate structures or complex bonding procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces corrosion risk, minimizes signal travel length, and optimizes space utilization, enabling smaller device sizes and faster signal transmission.
Implementation Method 1
forming a package substrate with conductive vias and interconnects using a laser-drilling process
Data Source
AI summary
Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having at least a first layer and a second layer, an interconnect extending through the package substrate, a stack of dies carried by the package substrate, and one or more wirebonds electrically coupling the stack of dies to package substrate. Each of the layers of the package substrate can include a section of the interconnect with a frustoconical shape. Each of the sections can be directly coupled together. Further, the section in an uppermost layer of the package substrate is exposed at an upper surface of the package substrate. The wirebonds can be directly coupled to the exposed surface of the uppermost section.