Direct-Write Wafer Level Package Ablation Process
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Solution Overview
Problem
Existing wafer level chip scale packaging techniques rely on photolithography, requiring photoimagable materials and complex masking and etching processes, which are costly, labor-intensive, and limited in flexibility and compliance between interconnections and silicon wafer surfaces.
Innovation Solution
The Direct Write Wafer Level Chip Scale Package method uses permanent dielectric and conductive layers applied directly to the wafer, with ablation to form patterns and vias, eliminating the need for photolithography and allowing for flexible thicknesses and adhesive layer usage, enabling multilayer structures with improved reliability and reduced costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography with photoimagable materials and masking/etching processes is used, then patterning can be achieved, but the process becomes costly, labor-intensive, and complex
Solution Approach 1:
The patent extracts and eliminates the photolithography step entirely from the packaging process. Instead of using photoimagable materials, masking, and etching, the invention directly patterns the dielectric layer through ablation or direct-write techniques, removing the complex photodefinition subsystem while maintaining patterning capability
Solution Approach 2:
The patent replaces the optical-mechanical photolithography system with a direct ablation or deposition system. The mechanical/thermal ablation process directly removes material to create patterns without requiring optical masks, photoresist chemicals, or complex alignment mechanisms
2Manufacturing precision
If photoimagable materials with limited thickness are used, then photolithography can be performed, but flexibility and compliance between interconnections and wafer surfaces are limited
Solution Approach 1:
The patent changes the thickness parameter of the dielectric layer from the limited range required by photolithography (less than 20 microns) to a much broader range that can be directly ablated or deposited. This parameter change enables the dielectric layer to provide compliance flexibility while still allowing precise pattern formation through ablation
Solution Approach 2:
Instead of constraining the dielectric layer thickness to match photolithography requirements, the patent inverts the approach by allowing the dielectric layer to be thicker and more flexible, then using ablation to achieve the required pattern precision after the layer is already in place
3Manufacturing precision
If multiple temporary masking layers are used, then patterning can be achieved, but material waste and process steps increase
Solution Approach 1:
The patent extracts and eliminates the temporary masking layers (photoresist, hard masks) from the process. The dielectric layer itself serves as the permanent structural element that is directly patterned through ablation, removing the need for multiple temporary material layers that must be deposited and subsequently removed
Solution Approach 2:
The patent eliminates the cycle of depositing temporary masking materials and then removing them as waste. The ablation process directly patterns the functional dielectric layer without requiring subsequent removal steps, thereby recovering the material utility and eliminating waste generation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces material costs and complexity, enhances flexibility and compliance between interconnections and silicon wafer surfaces, and facilitates the creation of reliable multilayer packages with improved thermal expansion properties.
Implementation Method 1
The dielectric layer is then ablated to form vias and trench patterns
Implementation Method 2
The surface of the dielectric layer is then plated with a conductive layer, such as copper, or another suitable metal
Data Source
AI summary
A method and structure provides a Direct Write Wafer Level Chip Scale Package (DWWLCSP) that utilizes permanent layers/coatings and direct write techniques to pattern these layers/coatings, thereby avoiding the use of photoimagable materials and photo-etching processes.