Disaggregated Memory Pooling With Dynamic Address Mapping
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Solution Overview
Problem
Disaggregated memory architectures in computing systems face increased latency and suboptimal performance due to high remote memory access penalties, limiting scalability and efficiency in resource utilization.
Innovation Solution
Implementing memory pooling circuitries (MPCs) with software-driven dynamic scheduling techniques to dynamically allocate and deallocate memory addresses across multiple CPUs, using a register like a translation lookaside buffer (TLB) to optimize memory utilization and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If disaggregated memory architecture is used to increase memory capacity and utilization, then memory bandwidth and utilization are improved, but access latency increases significantly
Solution Approach 1:
The system performs preliminary actions by predicting future memory access patterns and pre-loading data into local cache memory before it is actually needed. The memory controller monitors access patterns and proactively transfers data from disaggregated memory to local cache, reducing the latency penalty when hot data is needed by having it already available locally.
Solution Approach 2:
The patent introduces an intermediary layer (memory pooling circuitry with cache memory) between the CPU and disaggregated memory. This intermediary caches frequently accessed data locally, mediating between the high-speed local memory and the slower remote disaggregated memory, thus reducing access latency while maintaining the benefits of disaggregated architecture.
2Device complexity
If static memory allocation is used to simplify memory management, then device complexity is reduced, but adaptability to changing workload demands deteriorates
Solution Approach 1:
The system implements dynamic memory allocation where the memory controller continuously monitors workload demands and adjusts memory allocation accordingly. Memory regions are dynamically assigned to different CPUs based on real-time needs, and the cache allocation is dynamically adjusted based on observed access patterns, allowing the system to adapt to changing workload requirements without complex manual configuration.
Solution Approach 2:
The memory management system incorporates feedback mechanisms where access patterns are monitored and used to adjust allocation decisions. The system learns from historical access data and feedback from current workload demands to optimize memory allocation dynamically, balancing simplicity with adaptability through automated feedback-driven adjustments.
3Speed
If CPU caches are used to reduce remote memory access latency, then access speed is improved, but memory utilization efficiency deteriorates due to suboptimal caching strategies
Solution Approach 1:
The memory system implements self-service through automated cache management where the memory controller autonomously decides what data to cache and where to allocate memory based on observed access patterns. The system serves itself by automatically optimizing cache utilization without requiring external intervention or complex software management, improving both access speed and utilization efficiency through intelligent automated decision-making.
Data Source
AI summary
The apparatus of a disaggregated memory architecture (DMA) including a shared memory and multiple nodes is programmable by a primary node of the DMA. The primary node executes a programming agent to, prior to memory access requests to the shared memory, cause a programming of register entries of one or more registers of a memory pooling circuitry (MPC) with information to be used by a decoder of the MPC to translate host physical addresses (HPA) of memory access requests of the nodes to local memory addresses (LMAs). The LMAs are to be processed by one or more memory controllers (MCs) based on MC memory regions in each of the one or more MCs, the MC memory regions having a predetermined memory size granularity. At least some of the LMAs map to non-contiguous memory regions of the shared memory and of the one or more MCs.